From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53972) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqmYo-0000Ib-VJ for qemu-devel@nongnu.org; Wed, 11 Dec 2013 11:22:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VqmYj-0002NM-Uu for qemu-devel@nongnu.org; Wed, 11 Dec 2013 11:22:54 -0500 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:47982) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqmYj-0002NC-Pa for qemu-devel@nongnu.org; Wed, 11 Dec 2013 11:22:49 -0500 From: Aurelien Jarno Date: Wed, 11 Dec 2013 15:13:05 +0100 Message-Id: <1386771186-7442-4-git-send-email-aurelien@aurel32.net> In-Reply-To: <1386771186-7442-1-git-send-email-aurelien@aurel32.net> References: <1386771186-7442-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH v3 3/4] tcg/optimize: improve known-zero bits for 32-bit ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Aurelien Jarno The shl_i32 op might set some bits of the unused 32 high bits of the mask. Fix that by clearing the unused 32 high bits for all 32-bit ops except load/store which operate on tl values. Cc: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/optimize.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index 342c6e5..e14b564 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -787,6 +787,12 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, break; } + /* 32-bit ops (non 64-bit ops and non load/store ops) generate 32-bit + results */ + if (!(tcg_op_defs[op].flags & (TCG_OPF_CALL_CLOBBER | TCG_OPF_64BIT))) { + mask &= 0xffffffffu; + } + if (mask == 0) { assert(def->nb_oargs == 1); s->gen_opc_buf[op_index] = op_to_movi(op); -- 1.7.10.4