[Qemu-devel] [PATCH 0/5] target-s390: Use the new qemu_ld/st opcodes

[Qemu-devel] [PATCH 0/5] target-s390: Use the new qemu_ld/st opcodes

[Richard Henderson]

The first patch is purely mechanical.  The subsequent patches
tidy things up as allowed by the new interfaces.


r~


Richard Henderson (5):
  target-s390: Convert to new qemu_ld/st opcodes
  target-s390: Simplify op_clc
  target-s390: Simplify op_cs, op_soc, op_stm
  target-s390: Simplify op_icm, op_stcm
  target-s390: Use little-endian ops for LOAD/STORE REVERSED

 target-s390x/insn-data.def |  12 +--
 target-s390x/translate.c   | 251 ++++++++++++++++++++++-----------------------
 2 files changed, 130 insertions(+), 133 deletions(-)

-- 
1.8.3.1

[Qemu-devel] [PATCH 1/5] target-s390: Convert to new qemu_ld/st opcodes

[Richard Henderson]

Simplistic search and replace only.  Cleanups to follow.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-s390x/translate.c | 154 +++++++++++++++++++++++------------------------
 1 file changed, 77 insertions(+), 77 deletions(-)

diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index bc99a37..8fc8259 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -1754,20 +1754,20 @@ static ExitStatus op_clc(DisasContext *s, DisasOps *o)
 
     switch (l + 1) {
     case 1:
-        tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
-        tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
+        tcg_gen_qemu_ld_i64(cc_src, o->addr1, get_mem_index(s), MO_UB);
+        tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), MO_UB);
         break;
     case 2:
-        tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
-        tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
+        tcg_gen_qemu_ld_i64(cc_src, o->addr1, get_mem_index(s), MO_BEUW);
+        tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), MO_BEUW);
         break;
     case 4:
-        tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
-        tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
+        tcg_gen_qemu_ld_i64(cc_src, o->addr1, get_mem_index(s), MO_BEUL);
+        tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), MO_BEUL);
         break;
     case 8:
-        tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
-        tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
+        tcg_gen_qemu_ld_i64(cc_src, o->addr1, get_mem_index(s), MO_BEQ);
+        tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), MO_BEQ);
         break;
     default:
         potential_page_fault(s);
@@ -1841,9 +1841,9 @@ static ExitStatus op_cs(DisasContext *s, DisasOps *o)
        means that R1 is equal to the memory in all conditions.  */
     addr = get_address(s, 0, b2, d2);
     if (is_64) {
-        tcg_gen_qemu_ld64(o->out, addr, get_mem_index(s));
+        tcg_gen_qemu_ld_i64(o->out, addr, get_mem_index(s), MO_BEQ);
     } else {
-        tcg_gen_qemu_ld32u(o->out, addr, get_mem_index(s));
+        tcg_gen_qemu_ld_i64(o->out, addr, get_mem_index(s), MO_BEUL);
     }
 
     /* Are the memory and expected values (un)equal?  Note that this setcond
@@ -1859,9 +1859,9 @@ static ExitStatus op_cs(DisasContext *s, DisasOps *o)
     mem = tcg_temp_new_i64();
     tcg_gen_movcond_i64(TCG_COND_EQ, mem, cc, z, o->in1, o->out);
     if (is_64) {
-        tcg_gen_qemu_st64(mem, addr, get_mem_index(s));
+        tcg_gen_qemu_st_i64(mem, addr, get_mem_index(s), MO_BEQ);
     } else {
-        tcg_gen_qemu_st32(mem, addr, get_mem_index(s));
+        tcg_gen_qemu_st_i64(mem, addr, get_mem_index(s), MO_BEUL);
     }
     tcg_temp_free_i64(z);
     tcg_temp_free_i64(mem);
@@ -1891,8 +1891,8 @@ static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
     outh = tcg_temp_new_i64();
     outl = tcg_temp_new_i64();
 
-    tcg_gen_qemu_ld64(outh, addrh, get_mem_index(s));
-    tcg_gen_qemu_ld64(outl, addrl, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(outh, addrh, get_mem_index(s), MO_BEQ);
+    tcg_gen_qemu_ld_i64(outl, addrl, get_mem_index(s), MO_BEQ);
 
     /* Fold the double-word compare with arithmetic.  */
     cc = tcg_temp_new_i64();
@@ -1909,8 +1909,8 @@ static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
     tcg_gen_movcond_i64(TCG_COND_EQ, meml, cc, z, regs[r3 + 1], outl);
     tcg_temp_free_i64(z);
 
-    tcg_gen_qemu_st64(memh, addrh, get_mem_index(s));
-    tcg_gen_qemu_st64(meml, addrl, get_mem_index(s));
+    tcg_gen_qemu_st_i64(memh, addrh, get_mem_index(s), MO_BEQ);
+    tcg_gen_qemu_st_i64(meml, addrl, get_mem_index(s), MO_BEQ);
     tcg_temp_free_i64(memh);
     tcg_temp_free_i64(meml);
     tcg_temp_free_i64(addrh);
@@ -1946,7 +1946,7 @@ static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
     tcg_gen_trunc_i64_i32(t2, o->in1);
     gen_helper_cvd(t1, t2);
     tcg_temp_free_i32(t2);
-    tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
+    tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_BEQ);
     tcg_temp_free_i64(t1);
     return NO_EXIT;
 }
@@ -2110,7 +2110,7 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
     switch (m3) {
     case 0xf:
         /* Effectively a 32-bit load.  */
-        tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
+        tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUL);
         len = 32;
         goto one_insert;
 
@@ -2118,7 +2118,7 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
     case 0x6:
     case 0x3:
         /* Effectively a 16-bit load.  */
-        tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
+        tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUW);
         len = 16;
         goto one_insert;
 
@@ -2127,7 +2127,7 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
     case 0x2:
     case 0x1:
         /* Effectively an 8-bit load.  */
-        tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
+        tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
         len = 8;
         goto one_insert;
 
@@ -2143,7 +2143,7 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
         ccm = 0;
         while (m3) {
             if (m3 & 0x8) {
-                tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
+                tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
                 tcg_gen_addi_i64(o->in2, o->in2, 1);
                 tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
                 ccm |= 0xff << pos;
@@ -2249,43 +2249,43 @@ static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
 
 static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_SB);
     return NO_EXIT;
 }
 
 static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_UB);
     return NO_EXIT;
 }
 
 static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BESW);
     return NO_EXIT;
 }
 
 static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEUW);
     return NO_EXIT;
 }
 
 static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BESL);
     return NO_EXIT;
 }
 
 static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEUL);
     return NO_EXIT;
 }
 
 static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEQ);
     return NO_EXIT;
 }
 
@@ -2360,9 +2360,9 @@ static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
 
     t1 = tcg_temp_new_i64();
     t2 = tcg_temp_new_i64();
-    tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL);
     tcg_gen_addi_i64(o->in2, o->in2, 4);
-    tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_BEUL);
     /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK.  */
     tcg_gen_shli_i64(t1, t1, 32);
     gen_helper_load_psw(cpu_env, t1, t2);
@@ -2379,9 +2379,9 @@ static ExitStatus op_lpswe(DisasContext *s, DisasOps *o)
 
     t1 = tcg_temp_new_i64();
     t2 = tcg_temp_new_i64();
-    tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEQ);
     tcg_gen_addi_i64(o->in2, o->in2, 8);
-    tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_BEQ);
     gen_helper_load_psw(cpu_env, t1, t2);
     tcg_temp_free_i64(t1);
     tcg_temp_free_i64(t2);
@@ -2408,7 +2408,7 @@ static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
     TCGv_i64 t4 = tcg_const_i64(4);
 
     while (1) {
-        tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
+        tcg_gen_qemu_ld_i64(t, o->in2, get_mem_index(s), MO_BEUL);
         store_reg32_i64(r1, t);
         if (r1 == r3) {
             break;
@@ -2430,7 +2430,7 @@ static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
     TCGv_i64 t4 = tcg_const_i64(4);
 
     while (1) {
-        tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
+        tcg_gen_qemu_ld_i64(t, o->in2, get_mem_index(s), MO_BEUL);
         store_reg32h_i64(r1, t);
         if (r1 == r3) {
             break;
@@ -2451,7 +2451,7 @@ static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
     TCGv_i64 t8 = tcg_const_i64(8);
 
     while (1) {
-        tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
+        tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_BEQ);
         if (r1 == r3) {
             break;
         }
@@ -3015,9 +3015,9 @@ static ExitStatus op_soc(DisasContext *s, DisasOps *o)
     r1 = get_field(s->fields, r1);
     a = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
     if (s->insn->data) {
-        tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s));
+        tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_BEQ);
     } else {
-        tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s));
+        tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_BEUL);
     }
     tcg_temp_free_i64(a);
 
@@ -3162,9 +3162,9 @@ static ExitStatus op_stcke(DisasContext *s, DisasOps *o)
     tcg_gen_shli_i64(c2, c1, 56);
     tcg_gen_shri_i64(c1, c1, 8);
     tcg_gen_ori_i64(c2, c2, 0x10000);
-    tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
+    tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_BEQ);
     tcg_gen_addi_i64(o->in2, o->in2, 8);
-    tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
+    tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_BEQ);
     tcg_temp_free_i64(c1);
     tcg_temp_free_i64(c2);
     /* ??? We don't implement clock states.  */
@@ -3232,7 +3232,7 @@ static ExitStatus op_stfl(DisasContext *s, DisasOps *o)
     check_privileged(s);
     f = tcg_const_i64(0xc0000000);
     a = tcg_const_i64(200);
-    tcg_gen_qemu_st32(f, a, get_mem_index(s));
+    tcg_gen_qemu_st_i64(f, a, get_mem_index(s), MO_BEUL);
     tcg_temp_free_i64(f);
     tcg_temp_free_i64(a);
     return NO_EXIT;
@@ -3289,7 +3289,7 @@ static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
        restart, we'll have the wrong SYSTEM MASK in place.  */
     t = tcg_temp_new_i64();
     tcg_gen_shri_i64(t, psw_mask, 56);
-    tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
+    tcg_gen_qemu_st_i64(t, o->addr1, get_mem_index(s), MO_UB);
     tcg_temp_free_i64(t);
 
     if (s->fields->op == 0xac) {
@@ -3312,25 +3312,25 @@ static ExitStatus op_stura(DisasContext *s, DisasOps *o)
 
 static ExitStatus op_st8(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
+    tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_UB);
     return NO_EXIT;
 }
 
 static ExitStatus op_st16(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
+    tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_BEUW);
     return NO_EXIT;
 }
 
 static ExitStatus op_st32(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
+    tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_BEUL);
     return NO_EXIT;
 }
 
 static ExitStatus op_st64(DisasContext *s, DisasOps *o)
 {
-    tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
+    tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_BEQ);
     return NO_EXIT;
 }
 
@@ -3356,7 +3356,7 @@ static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
     case 0xf:
         /* Effectively a 32-bit store.  */
         tcg_gen_shri_i64(tmp, o->in1, pos);
-        tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
+        tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUL);
         break;
 
     case 0xc:
@@ -3364,7 +3364,7 @@ static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
     case 0x3:
         /* Effectively a 16-bit store.  */
         tcg_gen_shri_i64(tmp, o->in1, pos);
-        tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
+        tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUW);
         break;
 
     case 0x8:
@@ -3373,7 +3373,7 @@ static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
     case 0x1:
         /* Effectively an 8-bit store.  */
         tcg_gen_shri_i64(tmp, o->in1, pos);
-        tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
+        tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
         break;
 
     default:
@@ -3382,7 +3382,7 @@ static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
         while (m3) {
             if (m3 & 0x8) {
                 tcg_gen_shri_i64(tmp, o->in1, pos);
-                tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
+                tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
                 tcg_gen_addi_i64(o->in2, o->in2, 1);
             }
             m3 = (m3 << 1) & 0xf;
@@ -3403,9 +3403,9 @@ static ExitStatus op_stm(DisasContext *s, DisasOps *o)
 
     while (1) {
         if (size == 8) {
-            tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
+            tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s), MO_BEQ);
         } else {
-            tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
+            tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s), MO_BEUL);
         }
         if (r1 == r3) {
             break;
@@ -3428,7 +3428,7 @@ static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
 
     while (1) {
         tcg_gen_shl_i64(t, regs[r1], t32);
-        tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
+        tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_BEUL);
         if (r1 == r3) {
             break;
         }
@@ -3569,28 +3569,28 @@ static ExitStatus op_xc(DisasContext *s, DisasOps *o)
 
         l++;
         while (l >= 8) {
-            tcg_gen_qemu_st64(o->in2, o->addr1, get_mem_index(s));
+            tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_BEQ);
             l -= 8;
             if (l > 0) {
                 tcg_gen_addi_i64(o->addr1, o->addr1, 8);
             }
         }
         if (l >= 4) {
-            tcg_gen_qemu_st32(o->in2, o->addr1, get_mem_index(s));
+            tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_BEUL);
             l -= 4;
             if (l > 0) {
                 tcg_gen_addi_i64(o->addr1, o->addr1, 4);
             }
         }
         if (l >= 2) {
-            tcg_gen_qemu_st16(o->in2, o->addr1, get_mem_index(s));
+            tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_BEUW);
             l -= 2;
             if (l > 0) {
                 tcg_gen_addi_i64(o->addr1, o->addr1, 2);
             }
         }
         if (l) {
-            tcg_gen_qemu_st8(o->in2, o->addr1, get_mem_index(s));
+            tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UB);
         }
         gen_op_movi_cc(s, 0);
         return NO_EXIT;
@@ -3941,31 +3941,31 @@ static void wout_cond_e1e2(DisasContext *s, DisasFields *f, DisasOps *o)
 
 static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
 {
-    tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
+    tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_UB);
 }
 #define SPEC_wout_m1_8 0
 
 static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
 {
-    tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
+    tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUW);
 }
 #define SPEC_wout_m1_16 0
 
 static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
 {
-    tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
+    tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUL);
 }
 #define SPEC_wout_m1_32 0
 
 static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
 {
-    tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
+    tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEQ);
 }
 #define SPEC_wout_m1_64 0
 
 static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
 {
-    tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
+    tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_BEUL);
 }
 #define SPEC_wout_m2_32 0
 
@@ -4121,7 +4121,7 @@ static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in1_la1(s, f, o);
     o->in1 = tcg_temp_new_i64();
-    tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_UB);
 }
 #define SPEC_in1_m1_8u 0
 
@@ -4129,7 +4129,7 @@ static void in1_m1_16s(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in1_la1(s, f, o);
     o->in1 = tcg_temp_new_i64();
-    tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BESW);
 }
 #define SPEC_in1_m1_16s 0
 
@@ -4137,7 +4137,7 @@ static void in1_m1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in1_la1(s, f, o);
     o->in1 = tcg_temp_new_i64();
-    tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEUW);
 }
 #define SPEC_in1_m1_16u 0
 
@@ -4145,7 +4145,7 @@ static void in1_m1_32s(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in1_la1(s, f, o);
     o->in1 = tcg_temp_new_i64();
-    tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BESL);
 }
 #define SPEC_in1_m1_32s 0
 
@@ -4153,7 +4153,7 @@ static void in1_m1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in1_la1(s, f, o);
     o->in1 = tcg_temp_new_i64();
-    tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEUL);
 }
 #define SPEC_in1_m1_32u 0
 
@@ -4161,7 +4161,7 @@ static void in1_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in1_la1(s, f, o);
     o->in1 = tcg_temp_new_i64();
-    tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEQ);
 }
 #define SPEC_in1_m1_64 0
 
@@ -4323,70 +4323,70 @@ static void in2_sh64(DisasContext *s, DisasFields *f, DisasOps *o)
 static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in2_a2(s, f, o);
-    tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_UB);
 }
 #define SPEC_in2_m2_8u 0
 
 static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in2_a2(s, f, o);
-    tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BESW);
 }
 #define SPEC_in2_m2_16s 0
 
 static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in2_a2(s, f, o);
-    tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUW);
 }
 #define SPEC_in2_m2_16u 0
 
 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in2_a2(s, f, o);
-    tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BESL);
 }
 #define SPEC_in2_m2_32s 0
 
 static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in2_a2(s, f, o);
-    tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUL);
 }
 #define SPEC_in2_m2_32u 0
 
 static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in2_a2(s, f, o);
-    tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEQ);
 }
 #define SPEC_in2_m2_64 0
 
 static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in2_ri2(s, f, o);
-    tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUW);
 }
 #define SPEC_in2_mri2_16u 0
 
 static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in2_ri2(s, f, o);
-    tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BESL);
 }
 #define SPEC_in2_mri2_32s 0
 
 static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in2_ri2(s, f, o);
-    tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUL);
 }
 #define SPEC_in2_mri2_32u 0
 
 static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in2_ri2(s, f, o);
-    tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
+    tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEQ);
 }
 #define SPEC_in2_mri2_64 0
 
-- 
1.8.3.1

[Qemu-devel] [PATCH 2/5] target-s390: Simplify op_clc

[Richard Henderson]

New opcodes can unify 4 different code paths.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-s390x/translate.c | 30 +++++++++---------------------
 1 file changed, 9 insertions(+), 21 deletions(-)

diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 8fc8259..8f8567e 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -1750,34 +1750,22 @@ static ExitStatus op_cksm(DisasContext *s, DisasOps *o)
 static ExitStatus op_clc(DisasContext *s, DisasOps *o)
 {
     int l = get_field(s->fields, l1);
-    TCGv_i32 vl;
 
-    switch (l + 1) {
-    case 1:
-        tcg_gen_qemu_ld_i64(cc_src, o->addr1, get_mem_index(s), MO_UB);
-        tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), MO_UB);
-        break;
-    case 2:
-        tcg_gen_qemu_ld_i64(cc_src, o->addr1, get_mem_index(s), MO_BEUW);
-        tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), MO_BEUW);
-        break;
-    case 4:
-        tcg_gen_qemu_ld_i64(cc_src, o->addr1, get_mem_index(s), MO_BEUL);
-        tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), MO_BEUL);
-        break;
-    case 8:
-        tcg_gen_qemu_ld_i64(cc_src, o->addr1, get_mem_index(s), MO_BEQ);
-        tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), MO_BEQ);
-        break;
-    default:
+    if (l + 1 <= 8) {
+        TCGMemOp mop = MO_BE + ctz32(l + 1);
+
+        tcg_gen_qemu_ld_i64(cc_src, o->addr1, get_mem_index(s), mop);
+        tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), mop);
+        gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
+    } else {
+        TCGv_i32 vl;
+
         potential_page_fault(s);
         vl = tcg_const_i32(l);
         gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2);
         tcg_temp_free_i32(vl);
         set_cc_static(s);
-        return NO_EXIT;
     }
-    gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst);
     return NO_EXIT;
 }
 
-- 
1.8.3.1

[Qemu-devel] [PATCH 3/5] target-s390: Simplify op_cs, op_soc, op_stm

[Richard Henderson]

Unifying 2 different code paths each.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-s390x/translate.c | 28 +++++++---------------------
 1 file changed, 7 insertions(+), 21 deletions(-)

diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 8f8567e..3e88c23 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -1818,7 +1818,7 @@ static ExitStatus op_cs(DisasContext *s, DisasOps *o)
     /* FIXME: needs an atomic solution for CONFIG_USER_ONLY.  */
     int d2 = get_field(s->fields, d2);
     int b2 = get_field(s->fields, b2);
-    int is_64 = s->insn->data;
+    TCGMemOp mop = s->insn->data ? MO_BEQ : MO_BEUL;
     TCGv_i64 addr, mem, cc, z;
 
     /* Note that in1 = R3 (new value) and
@@ -1828,11 +1828,7 @@ static ExitStatus op_cs(DisasContext *s, DisasOps *o)
        about moving the memory to R1 on inequality, if we include equality it
        means that R1 is equal to the memory in all conditions.  */
     addr = get_address(s, 0, b2, d2);
-    if (is_64) {
-        tcg_gen_qemu_ld_i64(o->out, addr, get_mem_index(s), MO_BEQ);
-    } else {
-        tcg_gen_qemu_ld_i64(o->out, addr, get_mem_index(s), MO_BEUL);
-    }
+    tcg_gen_qemu_ld_i64(o->out, addr, get_mem_index(s), mop);
 
     /* Are the memory and expected values (un)equal?  Note that this setcond
        produces the output CC value, thus the NE sense of the test.  */
@@ -1846,11 +1842,7 @@ static ExitStatus op_cs(DisasContext *s, DisasOps *o)
     z = tcg_const_i64(0);
     mem = tcg_temp_new_i64();
     tcg_gen_movcond_i64(TCG_COND_EQ, mem, cc, z, o->in1, o->out);
-    if (is_64) {
-        tcg_gen_qemu_st_i64(mem, addr, get_mem_index(s), MO_BEQ);
-    } else {
-        tcg_gen_qemu_st_i64(mem, addr, get_mem_index(s), MO_BEUL);
-    }
+    tcg_gen_qemu_st_i64(mem, addr, get_mem_index(s), mop);
     tcg_temp_free_i64(z);
     tcg_temp_free_i64(mem);
     tcg_temp_free_i64(addr);
@@ -2986,6 +2978,7 @@ static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
 
 static ExitStatus op_soc(DisasContext *s, DisasOps *o)
 {
+    TCGMemOp mop = s->insn->data ? MO_BEQ : MO_BEUL;
     DisasCompare c;
     TCGv_i64 a;
     int lab, r1;
@@ -3002,11 +2995,7 @@ static ExitStatus op_soc(DisasContext *s, DisasOps *o)
 
     r1 = get_field(s->fields, r1);
     a = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
-    if (s->insn->data) {
-        tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_BEQ);
-    } else {
-        tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_BEUL);
-    }
+    tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), mop);
     tcg_temp_free_i64(a);
 
     gen_set_label(lab);
@@ -3387,14 +3376,11 @@ static ExitStatus op_stm(DisasContext *s, DisasOps *o)
     int r1 = get_field(s->fields, r1);
     int r3 = get_field(s->fields, r3);
     int size = s->insn->data;
+    TCGMemOp mop = size == 8 ? MO_BEQ : MO_BEUL;
     TCGv_i64 tsize = tcg_const_i64(size);
 
     while (1) {
-        if (size == 8) {
-            tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s), MO_BEQ);
-        } else {
-            tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s), MO_BEUL);
-        }
+        tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s), mop);
         if (r1 == r3) {
             break;
         }
-- 
1.8.3.1

[Qemu-devel] [PATCH 4/5] target-s390: Simplify op_icm, op_stcm

[Richard Henderson]

Loads and stores can now be shared, along with the surrounding code.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-s390x/translate.c | 27 ++++++++++++++++-----------
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 3e88c23..aa7d351 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -2085,12 +2085,13 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
     int m3 = get_field(s->fields, m3);
     int pos, len, base = s->insn->data;
     TCGv_i64 tmp = tcg_temp_new_i64();
+    TCGMemOp mop;
     uint64_t ccm;
 
     switch (m3) {
     case 0xf:
         /* Effectively a 32-bit load.  */
-        tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUL);
+        mop = MO_BEUL;
         len = 32;
         goto one_insert;
 
@@ -2098,7 +2099,7 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
     case 0x6:
     case 0x3:
         /* Effectively a 16-bit load.  */
-        tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUW);
+        mop = MO_BEUW;
         len = 16;
         goto one_insert;
 
@@ -2107,11 +2108,12 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
     case 0x2:
     case 0x1:
         /* Effectively an 8-bit load.  */
-        tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
+        mop = MO_UB;
         len = 8;
         goto one_insert;
 
     one_insert:
+        tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), mop);
         pos = base + ctz32(m3) * 8;
         tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
         ccm = ((1ull << len) - 1) << pos;
@@ -3327,30 +3329,33 @@ static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
     int m3 = get_field(s->fields, m3);
     int pos, base = s->insn->data;
     TCGv_i64 tmp = tcg_temp_new_i64();
+    TCGMemOp mop;
 
-    pos = base + ctz32(m3) * 8;
     switch (m3) {
     case 0xf:
         /* Effectively a 32-bit store.  */
-        tcg_gen_shri_i64(tmp, o->in1, pos);
-        tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUL);
-        break;
+        mop = MO_BEUL;
+        goto one_store;
 
     case 0xc:
     case 0x6:
     case 0x3:
         /* Effectively a 16-bit store.  */
-        tcg_gen_shri_i64(tmp, o->in1, pos);
-        tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUW);
-        break;
+        mop = MO_BEUW;
+        goto one_store;
 
     case 0x8:
     case 0x4:
     case 0x2:
     case 0x1:
         /* Effectively an 8-bit store.  */
+        mop = MO_UB;
+        goto one_store;
+
+    one_store:
+        pos = base + ctz32(m3) * 8;
         tcg_gen_shri_i64(tmp, o->in1, pos);
-        tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
+        tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), mop);
         break;
 
     default:
-- 
1.8.3.1

[Qemu-devel] [PATCH 5/5] target-s390: Use little-endian ops for LOAD/STORE REVERSED

[Richard Henderson]

We don't need separate bswap with the new qemu_ld/st opcodes.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-s390x/insn-data.def | 12 +++++-----
 target-s390x/translate.c   | 58 ++++++++++++++++++++++++++++++----------------
 2 files changed, 44 insertions(+), 26 deletions(-)

diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index b42ebb6..dade9ba 100644
--- a/target-s390x/insn-data.def
+++ b/target-s390x/insn-data.def
@@ -423,9 +423,9 @@
 /* LOAD REVERSED */
     C(0xb91f, LRVR,    RRE,   Z,   0, r2_32u, new, r1_32, rev32, 0)
     C(0xb90f, LRVGR,   RRE,   Z,   0, r2_o, r1, 0, rev64, 0)
-    C(0xe31f, LRVH,    RXY_a, Z,   0, m2_16u, new, r1_16, rev16, 0)
-    C(0xe31e, LRV,     RXY_a, Z,   0, m2_32u, new, r1_32, rev32, 0)
-    C(0xe30f, LRVG,    RXY_a, Z,   0, m2_64, r1, 0, rev64, 0)
+    C(0xe31f, LRVH,    RXY_a, Z,   0, a2, new, r1_16, ld16r, 0)
+    C(0xe31e, LRV,     RXY_a, Z,   0, a2, new, r1_32, ld32r, 0)
+    C(0xe30f, LRVG,    RXY_a, Z,   0, a2, r1, 0, ld64r, 0)
 /* LOAD ZERO */
     C(0xb374, LZER,    RRE,   Z,   0, 0, 0, e1, zero, 0)
     C(0xb375, LZDR,    RRE,   Z,   0, 0, 0, f1, zero, 0)
@@ -635,9 +635,9 @@
     D(0xebf3, STOC,    RSY_b, LOC, 0, 0, 0, 0, soc, 0, 0)
     D(0xebe3, STOCG,   RSY_b, LOC, 0, 0, 0, 0, soc, 0, 1)
 /* STORE REVERSED */
-    C(0xe33f, STRVH,   RXY_a, Z,   la2, r1_16u, new, m1_16, rev16, 0)
-    C(0xe33e, STRV,    RXY_a, Z,   la2, r1_32u, new, m1_32, rev32, 0)
-    C(0xe32f, STRVG,   RXY_a, Z,   la2, r1_o, new, m1_64, rev64, 0)
+    C(0xe33f, STRVH,   RXY_a, Z,   r1_o, a2, 0, 0, st16r, 0)
+    C(0xe33e, STRV,    RXY_a, Z,   r1_o, a2, 0, 0, st32r, 0)
+    C(0xe32f, STRVG,   RXY_a, Z,   r1_o, a2, 0, 0, st64r, 0)
 
 /* STORE FPC */
     C(0xb29c, STFPC,   S,     Z,   0, a2, new, m2_32, efpc, 0)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index aa7d351..f1c000d 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -2271,6 +2271,24 @@ static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_ld16r(DisasContext *s, DisasOps *o)
+{
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_LEUW);
+    return NO_EXIT;
+}
+
+static ExitStatus op_ld32r(DisasContext *s, DisasOps *o)
+{
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_LEUL);
+    return NO_EXIT;
+}
+
+static ExitStatus op_ld64r(DisasContext *s, DisasOps *o)
+{
+    tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_LEQ);
+    return NO_EXIT;
+}
+
 static ExitStatus op_loc(DisasContext *s, DisasOps *o)
 {
     DisasCompare c;
@@ -2855,12 +2873,6 @@ static ExitStatus op_rosbg(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
-static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
-{
-    tcg_gen_bswap16_i64(o->out, o->in2);
-    return NO_EXIT;
-}
-
 static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
 {
     tcg_gen_bswap32_i64(o->out, o->in2);
@@ -3313,6 +3325,24 @@ static ExitStatus op_st64(DisasContext *s, DisasOps *o)
     return NO_EXIT;
 }
 
+static ExitStatus op_st16r(DisasContext *s, DisasOps *o)
+{
+    tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_LEUW);
+    return NO_EXIT;
+}
+
+static ExitStatus op_st32r(DisasContext *s, DisasOps *o)
+{
+    tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_LEUL);
+    return NO_EXIT;
+}
+
+static ExitStatus op_st64r(DisasContext *s, DisasOps *o)
+{
+    tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_LEQ);
+    return NO_EXIT;
+}
+
 static ExitStatus op_stam(DisasContext *s, DisasOps *o)
 {
     TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
@@ -4089,12 +4119,14 @@ static void in1_la1(DisasContext *s, DisasFields *f, DisasOps *o)
 }
 #define SPEC_in1_la1 0
 
+#ifndef CONFIG_USER_ONLY
 static void in1_la2(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     int x2 = have_field(f, x2) ? get_field(f, x2) : 0;
     o->addr1 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
 }
 #define SPEC_in1_la2 0
+#endif
 
 static void in1_m1_8u(DisasContext *s, DisasFields *f, DisasOps *o)
 {
@@ -4154,13 +4186,6 @@ static void in2_r1_o(DisasContext *s, DisasFields *f, DisasOps *o)
 }
 #define SPEC_in2_r1_o 0
 
-static void in2_r1_16u(DisasContext *s, DisasFields *f, DisasOps *o)
-{
-    o->in2 = tcg_temp_new_i64();
-    tcg_gen_ext16u_i64(o->in2, regs[get_field(f, r1)]);
-}
-#define SPEC_in2_r1_16u 0
-
 static void in2_r1_32u(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     o->in2 = tcg_temp_new_i64();
@@ -4313,13 +4338,6 @@ static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
 }
 #define SPEC_in2_m2_16s 0
 
-static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
-{
-    in2_a2(s, f, o);
-    tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUW);
-}
-#define SPEC_in2_m2_16u 0
-
 static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
 {
     in2_a2(s, f, o);
-- 
1.8.3.1

Re: [Qemu-devel] [PATCH 0/5] target-s390: Use the new qemu_ld/st opcodes

[Alexander Graf]

On 11.12.2013, at 20:30, Richard Henderson <rth@twiddle.net> wrote:

> The first patch is purely mechanical.  The subsequent patches
> tidy things up as allowed by the new interfaces.

Reviewed-by: Alexander Graf <agraf@suse.de>


Alex