From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47664) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqpVO-00050a-Ow for qemu-devel@nongnu.org; Wed, 11 Dec 2013 14:31:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VqpVH-0004DX-11 for qemu-devel@nongnu.org; Wed, 11 Dec 2013 14:31:34 -0500 Received: from mail-qe0-x22a.google.com ([2607:f8b0:400d:c02::22a]:60954) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqpVG-0004DC-Te for qemu-devel@nongnu.org; Wed, 11 Dec 2013 14:31:26 -0500 Received: by mail-qe0-f42.google.com with SMTP id b4so5817311qen.29 for ; Wed, 11 Dec 2013 11:31:26 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Wed, 11 Dec 2013 11:30:46 -0800 Message-Id: <1386790247-14267-5-git-send-email-rth@twiddle.net> In-Reply-To: <1386790247-14267-1-git-send-email-rth@twiddle.net> References: <1386790247-14267-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 4/5] target-s390: Simplify op_icm, op_stcm List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: agraf@suse.de Loads and stores can now be shared, along with the surrounding code. Signed-off-by: Richard Henderson --- target-s390x/translate.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 3e88c23..aa7d351 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2085,12 +2085,13 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o) int m3 = get_field(s->fields, m3); int pos, len, base = s->insn->data; TCGv_i64 tmp = tcg_temp_new_i64(); + TCGMemOp mop; uint64_t ccm; switch (m3) { case 0xf: /* Effectively a 32-bit load. */ - tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUL); + mop = MO_BEUL; len = 32; goto one_insert; @@ -2098,7 +2099,7 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o) case 0x6: case 0x3: /* Effectively a 16-bit load. */ - tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUW); + mop = MO_BEUW; len = 16; goto one_insert; @@ -2107,11 +2108,12 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o) case 0x2: case 0x1: /* Effectively an 8-bit load. */ - tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB); + mop = MO_UB; len = 8; goto one_insert; one_insert: + tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), mop); pos = base + ctz32(m3) * 8; tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len); ccm = ((1ull << len) - 1) << pos; @@ -3327,30 +3329,33 @@ static ExitStatus op_stcm(DisasContext *s, DisasOps *o) int m3 = get_field(s->fields, m3); int pos, base = s->insn->data; TCGv_i64 tmp = tcg_temp_new_i64(); + TCGMemOp mop; - pos = base + ctz32(m3) * 8; switch (m3) { case 0xf: /* Effectively a 32-bit store. */ - tcg_gen_shri_i64(tmp, o->in1, pos); - tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUL); - break; + mop = MO_BEUL; + goto one_store; case 0xc: case 0x6: case 0x3: /* Effectively a 16-bit store. */ - tcg_gen_shri_i64(tmp, o->in1, pos); - tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUW); - break; + mop = MO_BEUW; + goto one_store; case 0x8: case 0x4: case 0x2: case 0x1: /* Effectively an 8-bit store. */ + mop = MO_UB; + goto one_store; + + one_store: + pos = base + ctz32(m3) * 8; tcg_gen_shri_i64(tmp, o->in1, pos); - tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB); + tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), mop); break; default: -- 1.8.3.1