From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35327) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VrVVh-0003JL-7B for qemu-devel@nongnu.org; Fri, 13 Dec 2013 11:22:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VrVVb-0000PN-8O for qemu-devel@nongnu.org; Fri, 13 Dec 2013 11:22:41 -0500 Received: from mx1.redhat.com ([209.132.183.28]:25321) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VrVVb-0000PC-0T for qemu-devel@nongnu.org; Fri, 13 Dec 2013 11:22:35 -0500 From: Igor Mammedov Date: Fri, 13 Dec 2013 17:22:06 +0100 Message-Id: <1386951736-929-2-git-send-email-imammedo@redhat.com> In-Reply-To: <1386951736-929-1-git-send-email-imammedo@redhat.com> References: <1386951736-929-1-git-send-email-imammedo@redhat.com> Subject: [Qemu-devel] [PATCH 01/11] acpi: piix4: remove not needed GPE0 mask List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: stefanha@redhat.com, mst@redhat.com, hutao@cn.fujitsu.com, jjherne@us.ibm.com, brogers@suse.com, kraxel@redhat.com, aliguori@amazon.com, kaneshige.kenji@jp.fujitsu.com, chen.fan.fnst@cn.fujitsu.com, pbonzini@redhat.com, lersek@redhat.com Hardcoded GPE0 mask isn't really needed. Since GPE0_STS initialized with all bits cleared and only QEMU itself can set bits there (i.e. guest can only clear bits in it). So guest can't triger SCI by setting _STS & _EN bits and there is not reason to mask out not supported _STS bits since they shouldn't be set by QEMU in the first place. Signed-off-by: Igor Mammedov --- hw/acpi/piix4.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 93849c8..b4caeab 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -122,8 +122,7 @@ static void pm_update_sci(PIIX4PMState *s) ACPI_BITMASK_POWER_BUTTON_ENABLE | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | ACPI_BITMASK_TIMER_ENABLE)) != 0) || - (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) & - (PIIX4_PCI_HOTPLUG_STATUS | PIIX4_CPU_HOTPLUG_STATUS)) != 0); + ((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) != 0); qemu_set_irq(s->irq, sci_level); /* schedule a timer interruption if needed */ -- 1.8.3.1