From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53492) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VrYNw-00034C-CW for qemu-devel@nongnu.org; Fri, 13 Dec 2013 14:26:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VrYNu-0007mm-KD for qemu-devel@nongnu.org; Fri, 13 Dec 2013 14:26:52 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43488) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VrYNu-0007mc-DC for qemu-devel@nongnu.org; Fri, 13 Dec 2013 14:26:50 -0500 From: Peter Maydell Date: Fri, 13 Dec 2013 19:17:54 +0000 Message-Id: <1386962282-6839-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v3 0/8] target-arm: A64 decoder set 3: loads, stores, misc integer List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Version 3 of the third set of A64 decoder patches (loads, stores, misc integer). (Fourth set is very nearly ready to roll, I just need to review the load/store exclusive patch.) Changes v2->v3: * added the non-temporal forms of LDP/STP (fixing a miscoded unallocated_encoding() codepath) * updated function names to follow convention that disas_foo are passed a uint32_t insn to decode and handle_foo are passed decoded field values Changes v1->v2: * merged ldp and stp into one function/patch * minor cleanup as per RTH review * use the new tcg ops for guest load/store * catch the missing UNALLOCATED cases for load/store * add missing returns after unallocated_encoding() calls in vector load/store decode * use tcg ops for mul[su]h thanks -- PMM Alex Bennée (6): target-arm: A64: add support for ld/st pair target-arm: A64: add support for ld/st unsigned imm target-arm: A64: add support for ld/st with reg offset target-arm: A64: add support for ld/st with index target-arm: A64: add support for add, addi, sub, subi target-arm: A64: add support for move wide instructions Alexander Graf (2): target-arm: A64: add support for 3 src data proc insns target-arm: A64: implement SVC, BRK target-arm/translate-a64.c | 1115 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1100 insertions(+), 15 deletions(-) -- 1.8.5