From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51409) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VrYFg-0004M2-Oz for qemu-devel@nongnu.org; Fri, 13 Dec 2013 14:18:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VrYFZ-0005Tv-Hd for qemu-devel@nongnu.org; Fri, 13 Dec 2013 14:18:20 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43462) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VrYFZ-0005T4-BE for qemu-devel@nongnu.org; Fri, 13 Dec 2013 14:18:13 -0500 From: Peter Maydell Date: Fri, 13 Dec 2013 19:18:00 +0000 Message-Id: <1386962282-6839-7-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1386962282-6839-1-git-send-email-peter.maydell@linaro.org> References: <1386962282-6839-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v3 6/8] target-arm: A64: add support for move wide instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson From: Alex Bennée This patch adds emulation for the mov wide instructions (MOVN, MOVZ, MOVK). Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/translate-a64.c | 51 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 00dd369..a6f1945 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1641,10 +1641,57 @@ static void disas_logic_imm(DisasContext *s, uint32_t insn) } } -/* Move wide (immediate) */ +/* + * C3.4.5 Move wide (immediate) + * + * 31 30 29 28 23 22 21 20 5 4 0 + * +--+-----+-------------+-----+----------------+------+ + * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd | + * +--+-----+-------------+-----+----------------+------+ + * + * sf: 0 -> 32 bit, 1 -> 64 bit + * opc: 00 -> N, 10 -> Z, 11 -> K + * hw: shift/16 (0,16, and sf only 32, 48) + */ static void disas_movw_imm(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + int rd = extract32(insn, 0, 5); + uint64_t imm = extract32(insn, 5, 16); + int sf = extract32(insn, 31, 1); + int opc = extract32(insn, 29, 2); + int pos = extract32(insn, 21, 2) << 4; + TCGv_i64 tcg_rd = cpu_reg(s, rd); + TCGv_i64 tcg_imm; + + if (!sf && (pos >= 32)) { + unallocated_encoding(s); + return; + } + + switch (opc) { + case 0: /* MOVN */ + case 2: /* MOVZ */ + imm <<= pos; + if (opc == 0) { + imm = ~imm; + } + if (!sf) { + imm &= 0xffffffffu; + } + tcg_gen_movi_i64(tcg_rd, imm); + break; + case 3: /* MOVK */ + tcg_imm = tcg_const_i64(imm); + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16); + tcg_temp_free_i64(tcg_imm); + if (!sf) { + tcg_gen_ext32u_i64(tcg_rd, tcg_rd); + } + break; + default: + unallocated_encoding(s); + break; + } } /* C3.4.2 Bitfield -- 1.8.5