From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52878) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vt1Gh-0005vb-Ud for qemu-devel@nongnu.org; Tue, 17 Dec 2013 15:29:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vt1Gg-00036z-Rh for qemu-devel@nongnu.org; Tue, 17 Dec 2013 15:29:27 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43642) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vt1Gg-00036h-K9 for qemu-devel@nongnu.org; Tue, 17 Dec 2013 15:29:26 -0500 From: Peter Maydell Date: Tue, 17 Dec 2013 20:28:28 +0000 Message-Id: <1387312160-12318-11-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1387312160-12318-1-git-send-email-peter.maydell@linaro.org> References: <1387312160-12318-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 10/62] target-arm: Define and use ARM_FEATURE_CBAR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Blue Swirl , qemu-devel@nongnu.org, Aurelien Jarno From: Peter Crosthwaite Some processors (notably A9 within Highbank) define and use the CP15 configuration base address (CBAR). This is vendor specific so its best implemented as a CPU property (otherwise we would need vendor specific child classes for every ARM implementation). This patch prepares support for converting CBAR reset value to a CPU property by moving the CP registration out of the CPU init fn, as registration will need to happen at realize time to pick up any property updates. The easiest way to do this is via definition of a new ARM_FEATURE to flag the existence of the register. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Message-id: 9f697ef1e2ee60a3b9ef971a7f3bc3fa6752a9b7.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- target-arm/cpu.c | 12 +++--------- target-arm/cpu.h | 1 + target-arm/helper.c | 9 +++++++++ 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index a03743f..f21e995 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -617,6 +617,7 @@ static void cortex_a9_initfn(Object *obj) * and valid configurations; we don't model A9UP). */ set_feature(&cpu->env, ARM_FEATURE_V7MP); + set_feature(&cpu->env, ARM_FEATURE_CBAR); cpu->midr = 0x410fc090; cpu->reset_fpsid = 0x41033090; cpu->mvfr0 = 0x11110222; @@ -639,15 +640,7 @@ static void cortex_a9_initfn(Object *obj) cpu->clidr = (1 << 27) | (1 << 24) | 3; cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ - { - ARMCPRegInfo cbar = { - .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, - .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, - .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) - }; - define_one_arm_cp_reg(cpu, &cbar); - define_arm_cp_regs(cpu, cortexa9_cp_reginfo); - } + define_arm_cp_regs(cpu, cortexa9_cp_reginfo); } #ifndef CONFIG_USER_ONLY @@ -686,6 +679,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CBAR); set_feature(&cpu->env, ARM_FEATURE_LPAE); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 00fd80d..c6c19e9 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -468,6 +468,7 @@ enum arm_features { ARM_FEATURE_V8, ARM_FEATURE_AARCH64, /* supports 64 bit mode */ ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ + ARM_FEATURE_CBAR, /* has cp15 CBAR */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target-arm/helper.c b/target-arm/helper.c index 71d6be3..cfbb14c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1745,6 +1745,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &auxcr); } + if (arm_feature(env, ARM_FEATURE_CBAR)) { + ARMCPRegInfo cbar = { + .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, + .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, + .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) + }; + define_one_arm_cp_reg(cpu, &cbar); + } + /* Generic registers whose values depend on the implementation */ { ARMCPRegInfo sctlr = { -- 1.8.5