From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33231) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vt1ol-0001y6-LE for qemu-devel@nongnu.org; Tue, 17 Dec 2013 16:04:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vt1ok-0005AC-EA for qemu-devel@nongnu.org; Tue, 17 Dec 2013 16:04:39 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43687) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vt1ok-0005A6-7x for qemu-devel@nongnu.org; Tue, 17 Dec 2013 16:04:38 -0500 From: Peter Maydell Date: Tue, 17 Dec 2013 20:28:34 +0000 Message-Id: <1387312160-12318-17-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1387312160-12318-1-git-send-email-peter.maydell@linaro.org> References: <1387312160-12318-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 16/62] arm/highbank.c: Fix MPCore periphbase name List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Blue Swirl , qemu-devel@nongnu.org, Aurelien Jarno From: Peter Crosthwaite GIC_BASE_ADDR is not the base address of the GIC. Its clear from the code that this is the base address of the MPCore. Rename to MPCORE_PERIPHBASE accordingly. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Message-id: 90798bd3507205c16238b8b19a1a58c5437cf7ca.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/arm/highbank.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index cb32325..c75b425 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -28,11 +28,11 @@ #include "exec/address-spaces.h" #include "qemu/error-report.h" -#define SMP_BOOT_ADDR 0x100 -#define SMP_BOOT_REG 0x40 -#define GIC_BASE_ADDR 0xfff10000 +#define SMP_BOOT_ADDR 0x100 +#define SMP_BOOT_REG 0x40 +#define MPCORE_PERIPHBASE 0xfff10000 -#define NIRQ_GIC 160 +#define NIRQ_GIC 160 /* Board init. */ @@ -55,7 +55,7 @@ static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) 0xe1110001, /* tst r1, r1 */ 0x0afffffb, /* beq */ 0xe12fff11, /* bx r1 */ - GIC_BASE_ADDR /* privbase: gic address. */ + MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */ }; for (n = 0; n < ARRAY_SIZE(smpboot); n++) { smpboot[n] = tswap32(smpboot[n]); @@ -236,7 +236,8 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine) cpu = ARM_CPU(object_new(object_class_get_name(oc))); - object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar", &err); + object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", + &err); if (err) { error_report("%s", error_get_pretty(err)); exit(1); @@ -287,7 +288,7 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine) qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); qdev_init_nofail(dev); busdev = SYS_BUS_DEVICE(dev); - sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR); + sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); for (n = 0; n < smp_cpus; n++) { sysbus_connect_irq(busdev, n, cpu_irq[n]); } -- 1.8.5