From: Peter Maydell <peter.maydell@linaro.org>
To: Anthony Liguori <aliguori@amazon.com>
Cc: Blue Swirl <blauwirbel@gmail.com>,
qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL 03/62] Add device-width property to pflash_cfi01
Date: Tue, 17 Dec 2013 20:28:21 +0000 [thread overview]
Message-ID: <1387312160-12318-4-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1387312160-12318-1-git-send-email-peter.maydell@linaro.org>
From: Roy Franz <roy.franz@linaro.org>
The width of the devices that make up the flash interface
is required to mask certain commands, in particular the
write length for buffered writes. This length will be presented
to each device on the interface by the program writing the flash,
and the flash emulation code needs to be able to determine
the length of the write as recieved by each flash device.
The device-width defaults to the bank width which should
maintain existing behavior for platforms that don't need
this change.
This change is required to support buffered writes on the
vexpress platform that has a 32 bit flash interface with 2
16 bit devices on it.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id: 1386279359-32286-3-git-send-email-roy.franz@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/block/pflash_cfi01.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index a0d7a16..a458ad6 100644
--- a/hw/block/pflash_cfi01.c
+++ b/hw/block/pflash_cfi01.c
@@ -40,6 +40,7 @@
#include "hw/block/flash.h"
#include "block/block.h"
#include "qemu/timer.h"
+#include "qemu/bitops.h"
#include "exec/address-spaces.h"
#include "qemu/host-utils.h"
#include "hw/sysbus.h"
@@ -72,6 +73,7 @@ struct pflash_t {
uint32_t nb_blocs;
uint64_t sector_len;
uint8_t bank_width;
+ uint8_t device_width; /* If 0, device width not specified. */
uint8_t be;
uint8_t wcycle; /* if 0, the flash is read normally */
int ro;
@@ -379,6 +381,14 @@ static void pflash_write(pflash_t *pfl, hwaddr offset,
break;
case 0xe8:
+ /* Mask writeblock size based on device width, or bank width if
+ * device width not specified.
+ */
+ if (pfl->device_width) {
+ value = extract32(value, 0, pfl->device_width * 8);
+ } else {
+ value = extract32(value, 0, pfl->bank_width * 8);
+ }
DPRINTF("%s: block write of %x bytes\n", __func__, value);
pfl->counter = value;
pfl->wcycle++;
@@ -708,6 +718,7 @@ static Property pflash_cfi01_properties[] = {
DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0),
DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0),
DEFINE_PROP_UINT8("width", struct pflash_t, bank_width, 0),
+ DEFINE_PROP_UINT8("device-width", struct pflash_t, device_width, 0),
DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0),
DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0),
DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0),
--
1.8.5
next prev parent reply other threads:[~2013-12-17 20:57 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-17 20:28 [Qemu-devel] [PULL 00/62] target-arm queue Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 01/62] target-arm: add support for v8 AES instructions Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 02/62] rename pflash_t member width to bank_width Peter Maydell
2013-12-17 20:28 ` Peter Maydell [this message]
2013-12-17 20:28 ` [Qemu-devel] [PULL 04/62] return status for each NOR flash device Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 05/62] Set proper device-width for vexpress flash Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 06/62] Add max device width parameter for NOR devices Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 07/62] Fix CFI query responses for NOR flash Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 08/62] Fix NOR flash device ID reading Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 09/62] target-arm/helper.c: Allow cp15.c15 dummy override Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 10/62] target-arm: Define and use ARM_FEATURE_CBAR Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 11/62] target-arm/cpu: Convert reset CBAR to a property Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 12/62] arm/highbank: Use object_new() rather than cpu_arm_init() Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 13/62] arm/highbank: Fix CBAR initialisation Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 14/62] arm/xilinx_zynq: Use object_new() rather than cpu_arm_init() Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 15/62] arm/xilinx_zynq: Implement CBAR initialisation Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 16/62] arm/highbank.c: Fix MPCore periphbase name Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 17/62] ARM: cpu: add "reset_hivecs" property Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 18/62] ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 19/62] target-arm/kvm: Split 32 bit only code into its own file Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 20/62] target-arm: Clean up handling of AArch64 PSTATE Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 21/62] target-arm: Add minimal KVM AArch64 support Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 22/62] configure: Enable KVM for aarch64 host/target combination Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 23/62] hw/arm/boot: Allow easier swapping in of different loader code Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 24/62] hw/arm/boot: Add boot support for AArch64 processor Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 25/62] default-configs: Add config for aarch64-softmmu Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 26/62] target-arm: Split A64 from A32/T32 gen_intermediate_code_internal() Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 27/62] target-arm: A64: add set_pc cpu method Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 28/62] target-arm: A64: provide functions for accessing FPCR and FPSR Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 29/62] target-arm: Support fp registers in gdb stub Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 30/62] target-arm: A64: add stubs for a64 specific helpers Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 31/62] target-arm: A64: provide skeleton for a64 insn decoding Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 32/62] target-arm: A64: expand decoding skeleton for system instructions Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 33/62] target-arm: A64: add support for B and BL insns Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 34/62] target-arm: A64: add support for BR, BLR and RET insns Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 35/62] target-arm: A64: add support for conditional branches Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 36/62] target-arm: A64: add support for 'test and branch' imm Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 37/62] target-arm: A64: add support for compare and branch imm Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 38/62] target-arm: A64: add support for conditional select Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 39/62] target-arm: A64: add support for logical (shifted register) Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 40/62] target-arm: A64: add support for ADR and ADRP Peter Maydell
2013-12-17 20:28 ` [Qemu-devel] [PULL 41/62] target-arm: A64: add support for EXTR Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 42/62] target-arm: A64: add support for 2-src data processing and DIV Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 43/62] target-arm: A64: add support for 2-src shift reg insns Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 44/62] target-arm: A64: add support for 1-src data processing and CLZ Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 45/62] target-arm: A64: add support for 1-src RBIT insn Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 46/62] target-arm: A64: add support for 1-src REV insns Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 47/62] target-arm: A64: add support for bitfield insns Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 48/62] host-utils: add clrsb32/64 - count leading redundant sign bits Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 49/62] target-arm: A64: add support for 1-src CLS insn Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 50/62] target-arm: A64: add support for logical (immediate) insns Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 51/62] hw/arm: add very initial support for Canon DIGIC SoC Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 52/62] hw/arm/digic: prepare DIGIC-based boards support Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 53/62] hw/arm/digic: add timer support Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 54/62] hw/arm/digic: add UART support Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 55/62] hw/arm/digic: add NOR ROM support Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 56/62] MAINTAINERS: Document 'Canon DIGIC' machine Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 57/62] vmstate: Add support for an array of ptimer_state * Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 58/62] hw/timer: add allwinner a10 timer Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 59/62] hw/intc: add allwinner A10 interrupt controller Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 60/62] hw/arm: add allwinner a10 SoC support Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 61/62] hw/arm: add cubieboard support Peter Maydell
2013-12-17 20:29 ` [Qemu-devel] [PULL 62/62] MAINTAINERS: add myself to maintain allwinner-a10 Peter Maydell
2013-12-20 0:14 ` [Qemu-devel] [PULL 00/62] target-arm queue Anthony Liguori
2013-12-20 0:31 ` Peter Maydell
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