From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53237) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VtO3q-0005T5-AU for qemu-devel@nongnu.org; Wed, 18 Dec 2013 15:49:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VtO3h-0004bT-DQ for qemu-devel@nongnu.org; Wed, 18 Dec 2013 15:49:41 -0500 From: Tom Musta Date: Wed, 18 Dec 2013 14:49:03 -0600 Message-Id: <1387399747-4994-11-git-send-email-tommusta@gmail.com> In-Reply-To: <1387399747-4994-1-git-send-email-tommusta@gmail.com> References: <1387399747-4994-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [V3 PATCH 10/14] target-ppc: Fix and enable fri[mnpz] List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Tom Musta , qemu-ppc@nongnu.org The fri* series of instructions was introduced prior to ISA 2.06 and is supported on Power7 and Power8 hardware. However, the instruction is still considered illegal in the P7 and P8 QEMU emulation models. This patch enables these instructions for the P7 and P8 machines. Also, the existing helper is modified to correctly handle some of the boundary cases (NaNs and the inexact flag). Signed-off-by: Tom Musta --- target-ppc/fpu_helper.c | 12 ++++++------ target-ppc/translate_init.c | 2 ++ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index 18b9bcd..981f002 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -668,18 +668,18 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg, if (unlikely(float64_is_signaling_nan(farg.d))) { /* sNaN round */ - farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN | - POWERPC_EXCP_FP_VXCVI, 1); - } else if (unlikely(float64_is_quiet_nan(farg.d) || - float64_is_infinity(farg.d))) { - /* qNan / infinity round */ - farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); + fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + farg.ll = float64_default_nan | 0x0008000000000000ul; } else { set_float_rounding_mode(rounding_mode, &env->fp_status); farg.ll = float64_round_to_int(farg.d, &env->fp_status); /* Restore rounding mode from FPSCR */ fpscr_set_rounding_mode(env); + + /* fri* does not set FPSCR[XX] */ + env->fp_status.float_exception_flags &= ~float_flag_inexact; } + helper_float_check_status(env); return farg.ll; } diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 491e56c..7bb9bbc 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7228,6 +7228,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | @@ -7265,6 +7266,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | -- 1.7.1