From: Tom Musta <tommusta@gmail.com>
To: qemu-devel@nongnu.org
Cc: Tom Musta <tommusta@gmail.com>, qemu-ppc@nongnu.org
Subject: [Qemu-devel] [V3 PATCH 05/14] target-ppc: Add ISA 2.06 divwe[u][o] Instructions
Date: Wed, 18 Dec 2013 14:48:58 -0600 [thread overview]
Message-ID: <1387399747-4994-6-git-send-email-tommusta@gmail.com> (raw)
In-Reply-To: <1387399747-4994-1-git-send-email-tommusta@gmail.com>
This patch addes the Signed and Unsigned Divide Word Extended
instructions which were introduced in Power ISA 2.06.
V2: Eliminating extraneous code in the overflow case per comments
from Richard Henderson. Fixed corner case bug in divweu (check
for (RA) >= (RB)).
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 70 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b274a15..3344fa9 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -984,6 +984,72 @@ GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
/* divw divw. divwo divwo. */
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
+
+#define GEN_DIVWE(op, signed, compute_ov) \
+static void gen_##op(DisasContext *ctx) \
+{ \
+ /* Need to use local temps because of the branches */ \
+ TCGv ra = tcg_temp_local_new(); \
+ TCGv rb = tcg_temp_local_new(); \
+ int lbl_ov = gen_new_label(); \
+ int lbl_rc = gen_new_label(); \
+ \
+ if (signed) { \
+ TCGv tmp0; \
+ /* divide by zero ? */ \
+ tcg_gen_ext32s_i64(rb, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_gen_brcondi_i64(TCG_COND_EQ, rb, 0, lbl_ov); \
+ tcg_gen_shli_i64(ra, cpu_gpr[rA(ctx->opcode)], 32); \
+ /* check for MIN div -1 */ \
+ int l3 = gen_new_label(); \
+ tcg_gen_brcondi_i64(TCG_COND_NE, rb, -1l, l3); \
+ tcg_gen_brcondi_i64(TCG_COND_EQ, ra, INT64_MIN, lbl_ov); \
+ gen_set_label(l3); \
+ tcg_gen_div_i64(cpu_gpr[rD(ctx->opcode)], ra, rb); \
+ tmp0 = tcg_temp_local_new(); \
+ /* does the result fit in 32 bits? */ \
+ tcg_gen_ext32s_i64(tmp0, cpu_gpr[rD(ctx->opcode)]); \
+ tcg_gen_brcond_i64(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], tmp0, \
+ lbl_ov); \
+ tcg_temp_free(tmp0); \
+ } else { /* unsigned */ \
+ /* divide by zero ? */ \
+ tcg_gen_ext32u_i64(rb, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_gen_brcondi_i64(TCG_COND_EQ, rb, 0, lbl_ov); \
+ /* is ra[32:63] >= rb[32:63] ? */ \
+ tcg_gen_ext32u_i64(ra, cpu_gpr[rA(ctx->opcode)]); \
+ tcg_gen_brcond_i64(TCG_COND_GEU, ra, rb, lbl_ov); \
+ tcg_gen_shli_i64(ra, cpu_gpr[rA(ctx->opcode)], 32); \
+ tcg_gen_divu_i64(cpu_gpr[rD(ctx->opcode)], ra, rb); \
+ } \
+ \
+ if (compute_ov) { \
+ tcg_gen_movi_tl(cpu_ov, 0); \
+ } \
+ tcg_gen_br(lbl_rc); \
+ \
+ gen_set_label(lbl_ov); /* overflow handling */ \
+ tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], 0); \
+ \
+ if (compute_ov) { \
+ tcg_gen_movi_tl(cpu_ov, 1); \
+ tcg_gen_movi_tl(cpu_so, 1); \
+ } \
+ \
+ gen_set_label(lbl_rc); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
+ } \
+ \
+ tcg_temp_free(ra); \
+ tcg_temp_free(rb); \
+}
+
+GEN_DIVWE(divweu, 0, 0);
+GEN_DIVWE(divweuo, 0, 1);
+GEN_DIVWE(divwe, 1, 0);
+GEN_DIVWE(divweo, 1, 1);
+
#if defined(TARGET_PPC64)
static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
@@ -9603,6 +9669,10 @@ GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
+GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0x00000000, PPC_NONE, PPC2_ISA206),
+GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0x00000000, PPC_NONE, PPC2_ISA206),
#if defined(TARGET_PPC64)
#undef GEN_INT_ARITH_DIVD
--
1.7.1
next prev parent reply other threads:[~2013-12-18 20:49 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-18 20:48 [Qemu-devel] [V3 PATCH 00/14] target-ppc: Base ISA V2.06 for Power7/Power8 Tom Musta
2013-12-18 20:48 ` [Qemu-devel] [V3 PATCH 01/14] target-ppc: Add Flag for Power ISA V2.06 Tom Musta
2013-12-24 15:11 ` Richard Henderson
2013-12-18 20:48 ` [Qemu-devel] [V3 PATCH 02/14] target-ppc: Add ISA2.06 bpermd Instruction Tom Musta
2013-12-24 15:17 ` Richard Henderson
2013-12-28 0:23 ` Scott Wood
2013-12-30 14:48 ` Richard Henderson
2013-12-30 15:43 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2013-12-30 16:23 ` Richard Henderson
2013-12-28 0:27 ` [Qemu-devel] " Scott Wood
2013-12-18 20:48 ` [Qemu-devel] [V3 PATCH 03/14] target-ppc: Add ISA2.06 divdeu[o] Instructions Tom Musta
2013-12-24 15:20 ` Richard Henderson
2013-12-28 0:30 ` [Qemu-devel] [Qemu-ppc] " Scott Wood
2014-01-03 19:24 ` Tom Musta
2014-01-03 19:43 ` Scott Wood
2013-12-18 20:48 ` [Qemu-devel] [V3 PATCH 04/14] target-ppc: Add ISA2.06 divde[o] Instructions Tom Musta
2013-12-24 15:22 ` Richard Henderson
2013-12-18 20:48 ` Tom Musta [this message]
2013-12-24 15:26 ` [Qemu-devel] [V3 PATCH 05/14] target-ppc: Add ISA 2.06 divwe[u][o] Instructions Richard Henderson
2013-12-18 20:48 ` [Qemu-devel] [V3 PATCH 06/14] target-ppc: Add ISA2.06 lbarx, lharx Instructions Tom Musta
2013-12-24 15:28 ` Richard Henderson
2013-12-18 20:49 ` [Qemu-devel] [V3 PATCH 07/14] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions Tom Musta
2013-12-24 15:31 ` Richard Henderson
2013-12-18 20:49 ` [Qemu-devel] [V3 PATCH 08/14] target-ppc: Add ISA2.06 Float to Integer Instructions Tom Musta
2013-12-24 15:36 ` Richard Henderson
2013-12-18 20:49 ` [Qemu-devel] [V3 PATCH 09/14] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions Tom Musta
2013-12-24 15:41 ` Richard Henderson
2013-12-18 20:49 ` [Qemu-devel] [V3 PATCH 10/14] target-ppc: Fix and enable fri[mnpz] Tom Musta
2013-12-24 16:02 ` Richard Henderson
2014-01-06 20:06 ` Tom Musta
2013-12-18 20:49 ` [Qemu-devel] [V3 PATCH 11/14] target-ppc: Add ISA 2.06 ftdiv Instruction Tom Musta
2013-12-24 16:06 ` Richard Henderson
2013-12-18 20:49 ` [Qemu-devel] [V3 PATCH 12/14] target-ppc: Add ISA 2.06 ftsqrt Tom Musta
2013-12-24 16:07 ` Richard Henderson
2013-12-18 20:49 ` [Qemu-devel] [V3 PATCH 13/14] target-ppc: Enable frsqrtes on Power7 and Power8 Tom Musta
2013-12-24 16:07 ` Richard Henderson
2013-12-18 20:49 ` [Qemu-devel] [V3 PATCH 14/14] target-ppc: Add ISA2.06 lfiwzx Instruction Tom Musta
2013-12-24 16:09 ` Richard Henderson
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