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From: Alexey Kardashevskiy <aik@ozlabs.ru>
To: qemu-devel@nongnu.org
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>,
	qemu-ppc@nongnu.org, Alexander Graf <agraf@suse.de>
Subject: [Qemu-devel] [PATCH 3/5] target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers
Date: Fri, 20 Dec 2013 17:41:32 +1100	[thread overview]
Message-ID: <1387521694-28623-4-git-send-email-aik@ozlabs.ru> (raw)
In-Reply-To: <1387521694-28623-1-git-send-email-aik@ozlabs.ru>

Assuming that "U" in SPR_UCTRL is for "user", there is inconsistency with
970 user manuals/P5-bookIV/PowerISA204 which define the number as:

                       priviledged
#   spr5-9 spr0-4 name mtspr mfspr len cat
136 00100  01000  CTRL   -    no    32  S
152 00100  11000  CTRL  yes    -    32  S

This swaps the numbers. No effect from this change is expected though.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
 target-ppc/cpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 4369e7c..51bcd4a 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1250,7 +1250,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
 #define SPR_MPC_EIE           (0x050)
 #define SPR_MPC_EID           (0x051)
 #define SPR_MPC_NRI           (0x052)
-#define SPR_CTRL              (0x088)
+#define SPR_UCTRL             (0x088)
 #define SPR_MPC_CMPA          (0x090)
 #define SPR_MPC_CMPB          (0x091)
 #define SPR_MPC_CMPC          (0x092)
@@ -1259,7 +1259,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
 #define SPR_MPC_DER           (0x095)
 #define SPR_MPC_COUNTA        (0x096)
 #define SPR_MPC_COUNTB        (0x097)
-#define SPR_UCTRL             (0x098)
+#define SPR_CTRL              (0x098)
 #define SPR_MPC_CMPE          (0x098)
 #define SPR_MPC_CMPF          (0x099)
 #define SPR_MPC_CMPG          (0x09A)
-- 
1.8.4.rc4

  parent reply	other threads:[~2013-12-20  6:42 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-20  6:41 [Qemu-devel] [PATCH 0/5] targe-ppc: 970/p5+/p7/p7+/p8 SPRs cleanup Alexey Kardashevskiy
2013-12-20  6:41 ` [Qemu-devel] [PATCH 1/5] target-ppc: fix LPCR SPR number Alexey Kardashevskiy
2013-12-20  6:41 ` [Qemu-devel] [PATCH 2/5] target-ppc: remove powerpc 970gx Alexey Kardashevskiy
2013-12-20  6:41 ` Alexey Kardashevskiy [this message]
2013-12-20  6:41 ` [Qemu-devel] [PATCH 4/5] target-ppc: remove embedded MMU SPRs from 970, P5+/7/7+/8 Alexey Kardashevskiy
2013-12-20  6:41 ` [Qemu-devel] [PATCH 5/5] target-ppc: remove unsupported SPRs from 970 and P5+ Alexey Kardashevskiy
2013-12-20 10:51 ` [Qemu-devel] [PATCH 0/5] targe-ppc: 970/p5+/p7/p7+/p8 SPRs cleanup Alexander Graf

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