From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57346) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VuFlG-0007uE-NA for qemu-devel@nongnu.org; Sat, 21 Dec 2013 01:10:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VuFl8-0002LZ-Av for qemu-devel@nongnu.org; Sat, 21 Dec 2013 01:10:06 -0500 Received: from mail-pd0-f177.google.com ([209.85.192.177]:52422) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VuFl8-0002LV-5O for qemu-devel@nongnu.org; Sat, 21 Dec 2013 01:09:58 -0500 Received: by mail-pd0-f177.google.com with SMTP id q10so3335840pdj.22 for ; Fri, 20 Dec 2013 22:09:57 -0800 (PST) From: Christoffer Dall Date: Fri, 20 Dec 2013 22:09:33 -0800 Message-Id: <1387606179-22709-3-git-send-email-christoffer.dall@linaro.org> In-Reply-To: <1387606179-22709-1-git-send-email-christoffer.dall@linaro.org> References: <1387606179-22709-1-git-send-email-christoffer.dall@linaro.org> Subject: [Qemu-devel] [RFC PATCH v4 2/8] hw: arm_gic: Introduce gic_set_priority function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvmarm@lists.cs.columbia.edu, Christoffer Dall , patches@linaro.org To make the code slightly cleaner to look at and make the save/restore code easier to understand, introduce this function to set the priority of interrupts. Reviewed-by: Peter Maydell Signed-off-by: Christoffer Dall --- hw/intc/arm_gic.c | 15 ++++++++++----- hw/intc/gic_internal.h | 1 + 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 27c258a..6c59650 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -168,6 +168,15 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu) return new_irq; } +void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val) +{ + if (irq < GIC_INTERNAL) { + s->priority1[irq][cpu] = val; + } else { + s->priority2[(irq) - GIC_INTERNAL] = val; + } +} + void gic_complete_irq(GICState *s, int cpu, int irq) { int update = 0; @@ -443,11 +452,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x400) + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; - if (irq < GIC_INTERNAL) { - s->priority1[irq][cpu] = value; - } else { - s->priority2[irq - GIC_INTERNAL] = value; - } + gic_set_priority(s, cpu, irq, value); } else if (offset < 0xc00) { /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the * annoying exception of the 11MPCore's GIC. diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index efac78d..8c02d58 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -61,5 +61,6 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu); void gic_complete_irq(GICState *s, int cpu, int irq); void gic_update(GICState *s); void gic_init_irqs_and_distributor(GICState *s, int num_irq); +void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); #endif /* !QEMU_ARM_GIC_INTERNAL_H */ -- 1.8.5