From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
patches@linaro.org, "Michael Matz" <matz@suse.de>,
"Alexander Graf" <agraf@suse.de>,
"Claudio Fontana" <claudio.fontana@linaro.org>,
"Dirk Mueller" <dmueller@suse.de>,
"Will Newton" <will.newton@linaro.org>,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.cs.columbia.edu,
"Christoffer Dall" <christoffer.dall@linaro.org>,
"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v2 11/25] target-arm: Pull "add one cpreg to hashtable" into its own function
Date: Sun, 22 Dec 2013 22:49:53 +0000 [thread overview]
Message-ID: <1387752607-23755-12-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1387752607-23755-1-git-send-email-peter.maydell@linaro.org>
define_one_arm_cp_reg_with_opaque() has a set of nested loops which
insert a cpreg entry into the hashtable for each of the possible
opc/crn/crm values allowed by wildcard specifications. We're about
to add an extra loop to this nesting, so pull the core of the loop
(which adds a single entry to the hashtable) out into its own
function for clarity.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 94 +++++++++++++++++++++++++++++------------------------
1 file changed, 52 insertions(+), 42 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6ebd7dc..d833163 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1937,6 +1937,57 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
return cpu_list;
}
+static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+ void *opaque, int crm, int opc1, int opc2)
+{
+ /* Private utility function for define_one_arm_cp_reg_with_opaque():
+ * add a single reginfo struct to the hash table.
+ */
+ uint32_t *key = g_new(uint32_t, 1);
+ ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
+ int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
+ *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
+ if (opaque) {
+ r2->opaque = opaque;
+ }
+ /* Make sure reginfo passed to helpers for wildcarded regs
+ * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
+ */
+ r2->crm = crm;
+ r2->opc1 = opc1;
+ r2->opc2 = opc2;
+ /* By convention, for wildcarded registers only the first
+ * entry is used for migration; the others are marked as
+ * NO_MIGRATE so we don't try to transfer the register
+ * multiple times. Special registers (ie NOP/WFI) are
+ * never migratable.
+ */
+ if ((r->type & ARM_CP_SPECIAL) ||
+ ((r->crm == CP_ANY) && crm != 0) ||
+ ((r->opc1 == CP_ANY) && opc1 != 0) ||
+ ((r->opc2 == CP_ANY) && opc2 != 0)) {
+ r2->type |= ARM_CP_NO_MIGRATE;
+ }
+
+ /* Overriding of an existing definition must be explicitly
+ * requested.
+ */
+ if (!(r->type & ARM_CP_OVERRIDE)) {
+ ARMCPRegInfo *oldreg;
+ oldreg = g_hash_table_lookup(cpu->cp_regs, key);
+ if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
+ fprintf(stderr, "Register redefined: cp=%d %d bit "
+ "crn=%d crm=%d opc1=%d opc2=%d, "
+ "was %s, now %s\n", r2->cp, 32 + 32 * is64,
+ r2->crn, r2->crm, r2->opc1, r2->opc2,
+ oldreg->name, r2->name);
+ g_assert_not_reached();
+ }
+ }
+ g_hash_table_insert(cpu->cp_regs, key, r2);
+}
+
+
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
const ARMCPRegInfo *r, void *opaque)
{
@@ -1977,48 +2028,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
for (crm = crmmin; crm <= crmmax; crm++) {
for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
- uint32_t *key = g_new(uint32_t, 1);
- ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
- int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
- *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
- if (opaque) {
- r2->opaque = opaque;
- }
- /* Make sure reginfo passed to helpers for wildcarded regs
- * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
- */
- r2->crm = crm;
- r2->opc1 = opc1;
- r2->opc2 = opc2;
- /* By convention, for wildcarded registers only the first
- * entry is used for migration; the others are marked as
- * NO_MIGRATE so we don't try to transfer the register
- * multiple times. Special registers (ie NOP/WFI) are
- * never migratable.
- */
- if ((r->type & ARM_CP_SPECIAL) ||
- ((r->crm == CP_ANY) && crm != 0) ||
- ((r->opc1 == CP_ANY) && opc1 != 0) ||
- ((r->opc2 == CP_ANY) && opc2 != 0)) {
- r2->type |= ARM_CP_NO_MIGRATE;
- }
-
- /* Overriding of an existing definition must be explicitly
- * requested.
- */
- if (!(r->type & ARM_CP_OVERRIDE)) {
- ARMCPRegInfo *oldreg;
- oldreg = g_hash_table_lookup(cpu->cp_regs, key);
- if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
- fprintf(stderr, "Register redefined: cp=%d %d bit "
- "crn=%d crm=%d opc1=%d opc2=%d, "
- "was %s, now %s\n", r2->cp, 32 + 32 * is64,
- r2->crn, r2->crm, r2->opc1, r2->opc2,
- oldreg->name, r2->name);
- g_assert_not_reached();
- }
- }
- g_hash_table_insert(cpu->cp_regs, key, r2);
+ add_cpreg_to_hashtable(cpu, r, opaque, crm, opc1, opc2);
}
}
}
--
1.8.5
next prev parent reply other threads:[~2013-12-22 22:56 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-22 22:49 [Qemu-devel] [PATCH v2 00/25] target-arm: A64 decoder sets 3 and 4: everything but fp & simd Peter Maydell
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 01/25] target-arm: A64: add support for ld/st pair Peter Maydell
2013-12-23 19:49 ` Richard Henderson
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 02/25] target-arm: A64: add support for ld/st unsigned imm Peter Maydell
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 03/25] target-arm: A64: add support for ld/st with reg offset Peter Maydell
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 04/25] target-arm: A64: add support for ld/st with index Peter Maydell
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 05/25] target-arm: A64: add support for add, addi, sub, subi Peter Maydell
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 06/25] target-arm: A64: add support for move wide instructions Peter Maydell
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 07/25] target-arm: A64: add support for 3 src data proc insns Peter Maydell
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 08/25] target-arm: A64: implement SVC, BRK Peter Maydell
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 09/25] target-arm: A64: Add decoder skeleton for FP instructions Peter Maydell
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 10/25] target-arm: A64: implement FMOV Peter Maydell
2013-12-22 22:49 ` Peter Maydell [this message]
2013-12-23 19:51 ` [Qemu-devel] [PATCH v2 11/25] target-arm: Pull "add one cpreg to hashtable" into its own function Richard Henderson
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 12/25] target-arm: Update generic cpreg code for AArch64 Peter Maydell
2014-01-02 1:51 ` Peter Crosthwaite
2014-01-02 10:23 ` Peter Maydell
2014-01-04 19:58 ` Peter Maydell
2014-01-05 2:44 ` Peter Crosthwaite
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 13/25] target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder Peter Maydell
2013-12-23 20:11 ` Richard Henderson
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 14/25] target-arm: A64: Implement MRS/MSR/SYS/SYSL Peter Maydell
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 15/25] target-arm: A64: Implement minimal set of EL0-visible sysregs Peter Maydell
2014-01-04 2:34 ` Peter Crosthwaite
2014-01-04 11:35 ` Peter Maydell
2014-01-04 13:39 ` Peter Crosthwaite
2014-01-04 13:32 ` Peter Crosthwaite
2014-01-04 14:11 ` Peter Maydell
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 16/25] target-arm: Widen thread-local register state fields to 64 bits Peter Maydell
2013-12-23 20:23 ` Richard Henderson
2013-12-22 22:49 ` [Qemu-devel] [PATCH v2 17/25] target-arm: A64: add support for add/sub with carry Peter Maydell
2013-12-22 22:50 ` [Qemu-devel] [PATCH v2 18/25] target-arm: A64: add support for conditional compare insns Peter Maydell
2013-12-23 20:37 ` Richard Henderson
2013-12-22 22:50 ` [Qemu-devel] [PATCH v2 19/25] target-arm: aarch64: add support for ld lit Peter Maydell
2013-12-22 22:50 ` [Qemu-devel] [PATCH v2 20/25] target-arm: Widen exclusive-access support struct fields to 64 bits Peter Maydell
2013-12-23 21:27 ` Richard Henderson
2013-12-22 22:50 ` [Qemu-devel] [PATCH v2 21/25] target-arm: A64: support for ld/st/cl exclusive Peter Maydell
2013-12-23 21:34 ` Richard Henderson
2013-12-22 22:50 ` [Qemu-devel] [PATCH v2 22/25] linux-user: AArch64: define TARGET_CLONE_BACKWARDS Peter Maydell
2013-12-23 21:41 ` Richard Henderson
2013-12-22 22:50 ` [Qemu-devel] [PATCH v2 23/25] linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext Peter Maydell
2013-12-23 21:43 ` Richard Henderson
2013-12-22 22:50 ` [Qemu-devel] [PATCH v2 24/25] .travis.yml: Add aarch64-* targets Peter Maydell
2013-12-22 22:50 ` [Qemu-devel] [PATCH v2 25/25] default-configs: Add config for aarch64-linux-user Peter Maydell
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