From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40718) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vv834-0006EP-TT for qemu-devel@nongnu.org; Mon, 23 Dec 2013 11:08:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vv82y-0000tt-O6 for qemu-devel@nongnu.org; Mon, 23 Dec 2013 11:08:06 -0500 Received: from mx1.redhat.com ([209.132.183.28]:55080) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vv82y-0000tl-97 for qemu-devel@nongnu.org; Mon, 23 Dec 2013 11:08:00 -0500 Date: Mon, 23 Dec 2013 18:11:55 +0200 From: "Michael S. Tsirkin" Message-ID: <1387815007-1272-9-git-send-email-mst@redhat.com> References: <1387815007-1272-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1387815007-1272-1-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PULL 08/19] acpi: piix4: remove not needed GPE0 mask List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Igor Mammedov , Anthony Liguori From: Igor Mammedov Hardcoded GPE0 mask isn't really needed. Since GPE0_STS initialized with all bits cleared and only QEMU itself can set bits there (i.e. guest can only clear bits in it). So guest can't triger SCI by setting _STS & _EN bits and there is not reason to mask out not supported _STS bits since they shouldn't be set by QEMU in the first place. Signed-off-by: Igor Mammedov Signed-off-by: Michael S. Tsirkin --- hw/acpi/piix4.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 93849c8..b4caeab 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -122,8 +122,7 @@ static void pm_update_sci(PIIX4PMState *s) ACPI_BITMASK_POWER_BUTTON_ENABLE | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | ACPI_BITMASK_TIMER_ENABLE)) != 0) || - (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) & - (PIIX4_PCI_HOTPLUG_STATUS | PIIX4_CPU_HOTPLUG_STATUS)) != 0); + ((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) != 0); qemu_set_irq(s->irq, sci_level); /* schedule a timer interruption if needed */ -- MST