From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54002) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvRZr-0005HY-Aa for qemu-devel@nongnu.org; Tue, 24 Dec 2013 07:59:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VvRZh-00040Y-9l for qemu-devel@nongnu.org; Tue, 24 Dec 2013 07:59:15 -0500 Received: from cantor2.suse.de ([195.135.220.15]:51982 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvRZh-0003zF-34 for qemu-devel@nongnu.org; Tue, 24 Dec 2013 07:59:05 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 24 Dec 2013 13:58:52 +0100 Message-Id: <1387889941-9896-2-git-send-email-afaerber@suse.de> In-Reply-To: <1387889941-9896-1-git-send-email-afaerber@suse.de> References: <1387889941-9896-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 01/10] cputlb: Use memset() when flushing entries List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Richard Henderson From: Richard Henderson The size of tlb_table is 4k on a 64-bit host. For overwriting memory at this size, cacheline tricks can help. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno Signed-off-by: Andreas F=C3=A4rber --- cputlb.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/cputlb.c b/cputlb.c index fff0afb..d2da404 100644 --- a/cputlb.c +++ b/cputlb.c @@ -33,13 +33,6 @@ /* statistics */ int tlb_flush_count; =20 -static const CPUTLBEntry s_cputlb_empty_entry =3D { - .addr_read =3D -1, - .addr_write =3D -1, - .addr_code =3D -1, - .addend =3D -1, -}; - /* NOTE: * If flush_global is true (the usual case), flush all tlb entries. * If flush_global is false, flush (at least) all tlb entries not @@ -55,7 +48,6 @@ static const CPUTLBEntry s_cputlb_empty_entry =3D { void tlb_flush(CPUArchState *env, int flush_global) { CPUState *cpu =3D ENV_GET_CPU(env); - int i; =20 #if defined(DEBUG_TLB) printf("tlb_flush:\n"); @@ -64,14 +56,7 @@ void tlb_flush(CPUArchState *env, int flush_global) links while we are modifying them */ cpu->current_tb =3D NULL; =20 - for (i =3D 0; i < CPU_TLB_SIZE; i++) { - int mmu_idx; - - for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - env->tlb_table[mmu_idx][i] =3D s_cputlb_empty_entry; - } - } - + memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *)); =20 env->tlb_flush_addr =3D -1; @@ -87,7 +72,7 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_ent= ry, target_ulong addr) (TARGET_PAGE_MASK | TLB_INVALID_MASK)) || addr =3D=3D (tlb_entry->addr_code & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - *tlb_entry =3D s_cputlb_empty_entry; + memset(tlb_entry, -1, sizeof(*tlb_entry)); } } =20 --=20 1.8.4