From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54014) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvRZs-0005IH-5g for qemu-devel@nongnu.org; Tue, 24 Dec 2013 07:59:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VvRZh-00040q-Cs for qemu-devel@nongnu.org; Tue, 24 Dec 2013 07:59:16 -0500 Received: from cantor2.suse.de ([195.135.220.15]:51989 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VvRZh-0003zS-2t for qemu-devel@nongnu.org; Tue, 24 Dec 2013 07:59:05 -0500 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 24 Dec 2013 13:58:54 +0100 Message-Id: <1387889941-9896-4-git-send-email-afaerber@suse.de> In-Reply-To: <1387889941-9896-1-git-send-email-afaerber@suse.de> References: <1387889941-9896-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 03/10] target-i386: Move apic_state field from CPUX86State to X86CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "open list:X86" , Gleb Natapov , "Michael S. Tsirkin" , Marcelo Tosatti , Anthony Liguori , Chen Fan , Paolo Bonzini , =?UTF-8?q?Andreas=20F=C3=A4rber?= From: Chen Fan This motion is preparing for refactoring vCPU APIC subsequently. Signed-off-by: Chen Fan Signed-off-by: Andreas F=C3=A4rber --- cpu-exec.c | 2 +- cpus.c | 5 ++--- hw/i386/kvmvapic.c | 8 +++----- hw/i386/pc.c | 17 ++++++++--------- target-i386/cpu-qom.h | 4 ++++ target-i386/cpu.c | 22 ++++++++++------------ target-i386/cpu.h | 4 ---- target-i386/helper.c | 12 ++++++------ target-i386/kvm.c | 23 ++++++++++------------- target-i386/misc_helper.c | 8 ++++---- 10 files changed, 48 insertions(+), 57 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 30cfa2a..2711c58 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -320,7 +320,7 @@ int cpu_exec(CPUArchState *env) #if !defined(CONFIG_USER_ONLY) if (interrupt_request & CPU_INTERRUPT_POLL) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_POLL; - apic_poll_irq(env->apic_state); + apic_poll_irq(x86_env_get_cpu(env)->apic_state); } #endif if (interrupt_request & CPU_INTERRUPT_INIT) { diff --git a/cpus.c b/cpus.c index 01d128d..ca4c59f 100644 --- a/cpus.c +++ b/cpus.c @@ -1458,12 +1458,11 @@ void qmp_inject_nmi(Error **errp) =20 CPU_FOREACH(cs) { X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; =20 - if (!env->apic_state) { + if (!cpu->apic_state) { cpu_interrupt(cs, CPU_INTERRUPT_NMI); } else { - apic_deliver_nmi(env->apic_state); + apic_deliver_nmi(cpu->apic_state); } } #elif defined(TARGET_S390X) diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 2d87600..300a299 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -366,7 +366,7 @@ static int vapic_enable(VAPICROMState *s, X86CPU *cpu= ) (((hwaddr)cpu_number) << VAPIC_CPU_SHIFT); cpu_physical_memory_rw(vapic_paddr + offsetof(VAPICState, enabled), (void *)&enabled, sizeof(enabled), 1); - apic_enable_vapic(cpu->env.apic_state, vapic_paddr); + apic_enable_vapic(cpu->apic_state, vapic_paddr); =20 s->state =3D VAPIC_ACTIVE; =20 @@ -496,12 +496,10 @@ static void vapic_enable_tpr_reporting(bool enable) }; CPUState *cs; X86CPU *cpu; - CPUX86State *env; =20 CPU_FOREACH(cs) { cpu =3D X86_CPU(cs); - env =3D &cpu->env; - info.apic =3D env->apic_state; + info.apic =3D cpu->apic_state; run_on_cpu(cs, vapic_do_enable_tpr_reporting, &info); } } @@ -700,7 +698,7 @@ static void vapic_write(void *opaque, hwaddr addr, ui= nt64_t data, default: case 4: if (!kvm_irqchip_in_kernel()) { - apic_poll_irq(env->apic_state); + apic_poll_irq(cpu->apic_state); } break; } diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 3cd8f38..963446f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -171,14 +171,15 @@ void cpu_smm_update(CPUX86State *env) /* IRQ handling */ int cpu_get_pic_interrupt(CPUX86State *env) { + X86CPU *cpu =3D x86_env_get_cpu(env); int intno; =20 - intno =3D apic_get_interrupt(env->apic_state); + intno =3D apic_get_interrupt(cpu->apic_state); if (intno >=3D 0) { return intno; } /* read the irq from the PIC */ - if (!apic_accept_pic_intr(env->apic_state)) { + if (!apic_accept_pic_intr(cpu->apic_state)) { return -1; } =20 @@ -190,15 +191,13 @@ static void pic_irq_request(void *opaque, int irq, = int level) { CPUState *cs =3D first_cpu; X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; =20 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); - if (env->apic_state) { + if (cpu->apic_state) { CPU_FOREACH(cs) { cpu =3D X86_CPU(cs); - env =3D &cpu->env; - if (apic_accept_pic_intr(env->apic_state)) { - apic_deliver_pic_intr(env->apic_state, level); + if (apic_accept_pic_intr(cpu->apic_state)) { + apic_deliver_pic_intr(cpu->apic_state, level); } } } else { @@ -908,7 +907,7 @@ DeviceState *cpu_get_current_apic(void) { if (current_cpu) { X86CPU *cpu =3D X86_CPU(current_cpu); - return cpu->env.apic_state; + return cpu->apic_state; } else { return NULL; } @@ -1002,7 +1001,7 @@ void pc_cpus_init(const char *cpu_model, DeviceStat= e *icc_bridge) } =20 /* map APIC MMIO area if CPU has APIC */ - if (cpu && cpu->env.apic_state) { + if (cpu && cpu->apic_state) { /* XXX: what if the base changes? */ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, APIC_DEFAULT_ADDRESS, 0x1000); diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index f4fab15..dbe3e29 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -82,6 +82,10 @@ typedef struct X86CPU { * capabilities) directly to the guest. */ bool enable_pmu; + + /* in order to simplify APIC support, we leave this pointer to the + user */ + struct DeviceState *apic_state; } X86CPU; =20 static inline X86CPU *x86_env_get_cpu(CPUX86State *env) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index bb98f6d..e20b0c8 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2449,7 +2449,7 @@ static void x86_cpu_reset(CPUState *s) #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ if (s->cpu_index =3D=3D 0) { - apic_designate_bsp(env->apic_state); + apic_designate_bsp(cpu->apic_state); } =20 s->halted =3D !cpu_is_bsp(cpu); @@ -2459,7 +2459,7 @@ static void x86_cpu_reset(CPUState *s) #ifndef CONFIG_USER_ONLY bool cpu_is_bsp(X86CPU *cpu) { - return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BS= P; + return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP; } =20 /* TODO: remove me, when reset over QOM tree is implemented */ @@ -2500,31 +2500,29 @@ static void x86_cpu_apic_create(X86CPU *cpu, Erro= r **errp) apic_type =3D "xen-apic"; } =20 - env->apic_state =3D qdev_try_create(qdev_get_parent_bus(dev), apic_t= ype); - if (env->apic_state =3D=3D NULL) { + cpu->apic_state =3D qdev_try_create(qdev_get_parent_bus(dev), apic_t= ype); + if (cpu->apic_state =3D=3D NULL) { error_setg(errp, "APIC device '%s' could not be created", apic_t= ype); return; } =20 object_property_add_child(OBJECT(cpu), "apic", - OBJECT(env->apic_state), NULL); - qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id); + OBJECT(cpu->apic_state), NULL); + qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id); /* TODO: convert to link<> */ - apic =3D APIC_COMMON(env->apic_state); + apic =3D APIC_COMMON(cpu->apic_state); apic->cpu =3D cpu; } =20 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) { - CPUX86State *env =3D &cpu->env; - - if (env->apic_state =3D=3D NULL) { + if (cpu->apic_state =3D=3D NULL) { return; } =20 - if (qdev_init(env->apic_state)) { + if (qdev_init(cpu->apic_state)) { error_setg(errp, "APIC device '%s' could not be initialized", - object_get_typename(OBJECT(env->apic_state))); + object_get_typename(OBJECT(cpu->apic_state))); return; } } diff --git a/target-i386/cpu.h b/target-i386/cpu.h index ea373e8..1d94a9d 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -895,10 +895,6 @@ typedef struct CPUX86State { int tsc_khz; void *kvm_xsave_buf; =20 - /* in order to simplify APIC support, we leave this pointer to the - user */ - struct DeviceState *apic_state; - uint64_t mcg_cap; uint64_t mcg_ctl; uint64_t mce_banks[MCE_BANKS_DEF*4]; diff --git a/target-i386/helper.c b/target-i386/helper.c index 7c196ff..8132ca8 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1241,14 +1241,16 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu= , int bank, =20 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access) { + X86CPU *cpu =3D x86_env_get_cpu(env); + if (kvm_enabled()) { env->tpr_access_type =3D access; =20 - cpu_interrupt(CPU(x86_env_get_cpu(env)), CPU_INTERRUPT_TPR); + cpu_interrupt(CPU(cpu), CPU_INTERRUPT_TPR); } else { cpu_restore_state(env, env->mem_io_pc); =20 - apic_handle_tpr_access_report(env->apic_state, env->eip, access)= ; + apic_handle_tpr_access_report(cpu->apic_state, env->eip, access)= ; } } #endif /* !CONFIG_USER_ONLY */ @@ -1295,14 +1297,12 @@ void do_cpu_init(X86CPU *cpu) cpu_reset(cs); cs->interrupt_request =3D sipi; env->pat =3D pat; - apic_init_reset(env->apic_state); + apic_init_reset(cpu->apic_state); } =20 void do_cpu_sipi(X86CPU *cpu) { - CPUX86State *env =3D &cpu->env; - - apic_sipi(env->apic_state); + apic_sipi(cpu->apic_state); } #else void do_cpu_init(X86CPU *cpu) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 1188482..7522e98 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1069,8 +1069,8 @@ static int kvm_put_sregs(X86CPU *cpu) sregs.cr3 =3D env->cr[3]; sregs.cr4 =3D env->cr[4]; =20 - sregs.cr8 =3D cpu_get_apic_tpr(env->apic_state); - sregs.apic_base =3D cpu_get_apic_base(env->apic_state); + sregs.cr8 =3D cpu_get_apic_tpr(cpu->apic_state); + sregs.apic_base =3D cpu_get_apic_base(cpu->apic_state); =20 sregs.efer =3D env->efer; =20 @@ -1619,8 +1619,7 @@ static int kvm_get_mp_state(X86CPU *cpu) =20 static int kvm_get_apic(X86CPU *cpu) { - CPUX86State *env =3D &cpu->env; - DeviceState *apic =3D env->apic_state; + DeviceState *apic =3D cpu->apic_state; struct kvm_lapic_state kapic; int ret; =20 @@ -1637,8 +1636,7 @@ static int kvm_get_apic(X86CPU *cpu) =20 static int kvm_put_apic(X86CPU *cpu) { - CPUX86State *env =3D &cpu->env; - DeviceState *apic =3D env->apic_state; + DeviceState *apic =3D cpu->apic_state; struct kvm_lapic_state kapic; =20 if (apic && kvm_irqchip_in_kernel()) { @@ -1962,7 +1960,7 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run= *run) } =20 DPRINTF("setting tpr\n"); - run->cr8 =3D cpu_get_apic_tpr(env->apic_state); + run->cr8 =3D cpu_get_apic_tpr(x86_cpu->apic_state); } } =20 @@ -1976,8 +1974,8 @@ void kvm_arch_post_run(CPUState *cpu, struct kvm_ru= n *run) } else { env->eflags &=3D ~IF_MASK; } - cpu_set_apic_tpr(env->apic_state, run->cr8); - cpu_set_apic_base(env->apic_state, run->apic_base); + cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8); + cpu_set_apic_base(x86_cpu->apic_state, run->apic_base); } =20 int kvm_arch_process_async_events(CPUState *cs) @@ -2014,7 +2012,7 @@ int kvm_arch_process_async_events(CPUState *cs) =20 if (cs->interrupt_request & CPU_INTERRUPT_POLL) { cs->interrupt_request &=3D ~CPU_INTERRUPT_POLL; - apic_poll_irq(env->apic_state); + apic_poll_irq(cpu->apic_state); } if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) || @@ -2032,7 +2030,7 @@ int kvm_arch_process_async_events(CPUState *cs) if (cs->interrupt_request & CPU_INTERRUPT_TPR) { cs->interrupt_request &=3D ~CPU_INTERRUPT_TPR; kvm_cpu_synchronize_state(cs); - apic_handle_tpr_access_report(env->apic_state, env->eip, + apic_handle_tpr_access_report(cpu->apic_state, env->eip, env->tpr_access_type); } =20 @@ -2056,11 +2054,10 @@ static int kvm_handle_halt(X86CPU *cpu) =20 static int kvm_handle_tpr_access(X86CPU *cpu) { - CPUX86State *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); struct kvm_run *run =3D cs->kvm_run; =20 - apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip, + apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip, run->tpr_access.is_write ? TPR_ACCESS_= WRITE : TPR_ACCESS_= READ); return 1; diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index b6307ca..47f6a2f 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -155,7 +155,7 @@ target_ulong helper_read_crN(CPUX86State *env, int re= g) break; case 8: if (!(env->hflags2 & HF2_VINTR_MASK)) { - val =3D cpu_get_apic_tpr(env->apic_state); + val =3D cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state); } else { val =3D env->v_tpr; } @@ -179,7 +179,7 @@ void helper_write_crN(CPUX86State *env, int reg, targ= et_ulong t0) break; case 8: if (!(env->hflags2 & HF2_VINTR_MASK)) { - cpu_set_apic_tpr(env->apic_state, t0); + cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0); } env->v_tpr =3D t0 & 0x0f; break; @@ -286,7 +286,7 @@ void helper_wrmsr(CPUX86State *env) env->sysenter_eip =3D val; break; case MSR_IA32_APICBASE: - cpu_set_apic_base(env->apic_state, val); + cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val); break; case MSR_EFER: { @@ -437,7 +437,7 @@ void helper_rdmsr(CPUX86State *env) val =3D env->sysenter_eip; break; case MSR_IA32_APICBASE: - val =3D cpu_get_apic_base(env->apic_state); + val =3D cpu_get_apic_base(x86_env_get_cpu(env)->apic_state); break; case MSR_EFER: val =3D env->efer; --=20 1.8.4