From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40703) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vx1sK-0002Vp-Tc for qemu-devel@nongnu.org; Sat, 28 Dec 2013 16:56:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vx1sI-0007EK-Ug for qemu-devel@nongnu.org; Sat, 28 Dec 2013 16:56:52 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43947) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vx1sI-0007EA-O6 for qemu-devel@nongnu.org; Sat, 28 Dec 2013 16:56:50 -0500 From: Peter Maydell Date: Sat, 28 Dec 2013 21:49:02 +0000 Message-Id: <1388267351-31818-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1388267351-31818-1-git-send-email-peter.maydell@linaro.org> References: <1388267351-31818-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 01/10] target-arm: A64: Add support for dumping AArch64 VFP register state List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson From: Alexander Graf When dumping the current CPU state, we can also get a request to dump the FPU state along with the CPU's integer state. Add support to dump the VFP state when that flag is set, so that we can properly debug code that modifies floating point registers. Signed-off-by: Alexander Graf [WN: Commit message tweak, rebased. Output all registers, two per-line.] Signed-off-by: Will Newton Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 40c6fc4..6f2b26e 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -119,6 +119,22 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, psr & PSTATE_C ? 'C' : '-', psr & PSTATE_V ? 'V' : '-'); cpu_fprintf(f, "\n"); + + if (flags & CPU_DUMP_FPU) { + int numvfpregs = 32; + for (i = 0; i < numvfpregs; i += 2) { + uint64_t vlo = float64_val(env->vfp.regs[i * 2]); + uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]); + cpu_fprintf(f, "q%02d.0=%016" PRIx64 ":%016" PRIx64 " ", + i, vlo, vhi); + vlo = float64_val(env->vfp.regs[(i + 1) * 2]); + vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]); + cpu_fprintf(f, "q%02d.0=%016" PRIx64 ":%016" PRIx64 "\n", + i + 1, vlo, vhi); + } + cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n", + vfp_get_fpcr(env), vfp_get_fpsr(env)); + } } static int get_mem_index(DisasContext *s) -- 1.8.5