From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40708) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vx1sL-0002Vq-2d for qemu-devel@nongnu.org; Sat, 28 Dec 2013 16:56:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vx1sJ-0007Eh-Rs for qemu-devel@nongnu.org; Sat, 28 Dec 2013 16:56:53 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:43947) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vx1sJ-0007EA-Kh for qemu-devel@nongnu.org; Sat, 28 Dec 2013 16:56:51 -0500 From: Peter Maydell Date: Sat, 28 Dec 2013 21:49:07 +0000 Message-Id: <1388267351-31818-7-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1388267351-31818-1-git-send-email-peter.maydell@linaro.org> References: <1388267351-31818-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 06/10] target-arm: A64: Add fmov (scalar, immediate) instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson From: Alexander Graf This patch adds emulation for the fmov instruction working on scalars with an immediate payload. Signed-off-by: Alexander Graf [WN: Commit message tweak, rebase and use new infrastructure.] Signed-off-by: Will Newton Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index db24c87..107f3c6 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -3494,7 +3494,37 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn) */ static void disas_fp_imm(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + int rd = extract32(insn, 0, 5); + int imm8 = extract32(insn, 13, 8); + int is_double = extract32(insn, 22, 2); + uint64_t imm; + TCGv_i64 tcg_res; + + if (is_double > 1) { + unallocated_encoding(s); + return; + } + + /* The imm8 encodes the sign bit, enough bits to represent + * an exponent in the range 01....1xx to 10....0xx, + * and the most significant 4 bits of the mantissa; see + * VFPExpandImm() in the v8 ARM ARM. + */ + if (is_double) { + imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | + (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | + extract32(imm8, 0, 6); + imm <<= 48; + } else { + imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | + (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | + (extract32(imm8, 0, 6) << 3); + imm <<= 16; + } + + tcg_res = tcg_const_i64(imm); + write_fp_dreg(s, rd, tcg_res); + tcg_temp_free_i64(tcg_res); } /* C3.6.29 Floating point <-> fixed point conversions -- 1.8.5