From: Igor Mammedov <imammedo@redhat.com>
To: qemu-devel@nongnu.org
Cc: mst@redhat.com, hutao@cn.fujitsu.com, mjt@tls.msk.ru,
chen.fan.fnst@cn.fujitsu.com, kraxel@redhat.com,
anthony.perard@citrix.com, lersek@redhat.com, afaerber@suse.de
Subject: [Qemu-devel] [PATCH 2/9] acpi: ich9: add CPU hotplug handling to Q35 machine
Date: Sat, 28 Dec 2013 23:30:45 +0100 [thread overview]
Message-ID: <1388269852-21198-3-git-send-email-imammedo@redhat.com> (raw)
In-Reply-To: <1388269852-21198-1-git-send-email-imammedo@redhat.com>
.. use IO port 0xcd8-0xcf7 range for CPU present bitmap
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
---
docs/specs/acpi_cpu_hotplug.txt | 4 +++-
hw/acpi/ich9.c | 16 ++++++++++++++++
include/hw/acpi/ich9.h | 4 ++++
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.txt
index f6f5774..340b751 100644
--- a/docs/specs/acpi_cpu_hotplug.txt
+++ b/docs/specs/acpi_cpu_hotplug.txt
@@ -10,7 +10,9 @@ ACPI GPE block (IO ports 0xafe0-0xafe3, byte access):
Generic ACPI GPE block. Bit 2 (GPE.2) used to notify CPU
hot-add/remove event to ACPI BIOS, via SCI interrupt.
-CPU present bitmap (IO port 0xaf00-0xaf1f, 1-byte access):
+CPU present bitmap for:
+ ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
+ PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
---------------------------------------------------------------
One bit per CPU. Bit position reflects corresponding CPU APIC ID.
Read-only.
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index 30f0df8..03dee35 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -44,6 +44,8 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
#define ICH9_DEBUG(fmt, ...) do { } while (0)
#endif
+#define ICH9_PROC_BASE 0x0CD8
+
static void ich9_pm_update_sci_fn(ACPIREGS *regs)
{
ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
@@ -185,6 +187,15 @@ static void pm_powerdown_req(Notifier *n, void *opaque)
acpi_pm1_evt_power_down(&pm->acpi_regs);
}
+static void ich9_cpu_added_req(Notifier *n, void *opaque)
+{
+ ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, cpu_added_notifier);
+
+ assert(pm != NULL);
+ AcpiCpuHotplug_add(&pm->acpi_regs.gpe, &pm->gpe_cpu, CPU(opaque));
+ acpi_update_sci(&pm->acpi_regs, pm->irq);
+}
+
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
qemu_irq sci_irq)
{
@@ -210,6 +221,11 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
qemu_register_reset(pm_reset, pm);
pm->powerdown_notifier.notify = pm_powerdown_req;
qemu_register_powerdown_notifier(&pm->powerdown_notifier);
+
+ AcpiCpuHotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
+ &pm->gpe_cpu, ICH9_PROC_BASE);
+ pm->cpu_added_notifier.notify = ich9_cpu_added_req;
+ qemu_register_cpu_added_notifier(&pm->cpu_added_notifier);
}
static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v,
diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h
index 82fcf9f..104f419 100644
--- a/include/hw/acpi/ich9.h
+++ b/include/hw/acpi/ich9.h
@@ -22,6 +22,7 @@
#define HW_ACPI_ICH9_H
#include "hw/acpi/acpi.h"
+#include "hw/acpi/cpu_hotplug.h"
typedef struct ICH9LPCPMRegs {
/*
@@ -42,6 +43,9 @@ typedef struct ICH9LPCPMRegs {
uint32_t pm_io_base;
Notifier powerdown_notifier;
+
+ AcpiCpuHotplug gpe_cpu;
+ Notifier cpu_added_notifier;
} ICH9LPCPMRegs;
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
--
1.8.4.2
next prev parent reply other threads:[~2013-12-28 22:31 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-28 22:30 [Qemu-devel] [PATCH 0/9 v2] pc: CPU hotplug support for Q35 Igor Mammedov
2013-12-28 22:30 ` [Qemu-devel] [PATCH 1/9] acpi: factor out common cpu hotplug code for PIIX4/Q35 Igor Mammedov
2013-12-28 22:30 ` Igor Mammedov [this message]
2013-12-28 22:30 ` [Qemu-devel] [PATCH 3/9] pc: rebuild ACPI hex files if included *.dsl are touched Igor Mammedov
2014-01-08 17:47 ` Michael S. Tsirkin
2014-01-09 9:25 ` Igor Mammedov
2013-12-28 22:30 ` [Qemu-devel] [PATCH 4/9] pc: set PRST base in DSDT depending on chipset Igor Mammedov
2013-12-28 22:30 ` [Qemu-devel] [PATCH 5/9] pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resources Igor Mammedov
2014-01-08 17:00 ` Michael S. Tsirkin
2014-01-09 10:34 ` Igor Mammedov
2014-01-09 10:57 ` Michael S. Tsirkin
2013-12-28 22:30 ` [Qemu-devel] [PATCH 6/9] pc: Q35 DSDT: exclude CPU hotplug " Igor Mammedov
2013-12-28 22:30 ` [Qemu-devel] [PATCH 7/9] pc: ACPI: expose PRST IO range via _CRS Igor Mammedov
2014-01-08 16:50 ` Michael S. Tsirkin
2013-12-28 22:30 ` [Qemu-devel] [PATCH 8/9] pc: ACPI: unify source of CPU hotplug IO base/len Igor Mammedov
2014-01-08 17:06 ` Michael S. Tsirkin
2013-12-28 22:30 ` [Qemu-devel] [PATCH 9/9] pc: ACPI: update acpi-dsdt.hex.generated q35-acpi-dsdt.hex.generated Igor Mammedov
2014-01-08 17:47 ` [Qemu-devel] [PATCH 0/9 v2] pc: CPU hotplug support for Q35 Michael S. Tsirkin
-- strict thread matches above, loose matches on Subject: below --
2014-01-09 16:36 [Qemu-devel] [PATCH 0/9 v3] " Igor Mammedov
2014-01-09 16:36 ` [Qemu-devel] [PATCH 2/9] acpi: ich9: add CPU hotplug handling to Q35 machine Igor Mammedov
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