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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
	patches@linaro.org, "Michael Matz" <matz@suse.de>,
	"Alexander Graf" <agraf@suse.de>,
	"Claudio Fontana" <claudio.fontana@linaro.org>,
	"Dirk Mueller" <dmueller@suse.de>,
	"Will Newton" <will.newton@linaro.org>,
	"Laurent Desnogues" <laurent.desnogues@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	kvmarm@lists.cs.columbia.edu,
	"Christoffer Dall" <christoffer.dall@linaro.org>,
	"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v2 06/10] target-arm: A64: Add fmov (scalar, immediate) instruction
Date: Mon, 30 Dec 2013 16:34:31 +0000	[thread overview]
Message-ID: <1388421275-2035-7-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1388421275-2035-1-git-send-email-peter.maydell@linaro.org>

From: Alexander Graf <agraf@suse.de>

This patch adds emulation for the fmov instruction working on scalars
with an immediate payload.

Signed-off-by: Alexander Graf <agraf@suse.de>
[WN: Commit message tweak, rebase and use new infrastructure.]
Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
 target-arm/translate-a64.c | 32 +++++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 84497dc..bb36a66 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3479,7 +3479,37 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
  */
 static void disas_fp_imm(DisasContext *s, uint32_t insn)
 {
-    unsupported_encoding(s, insn);
+    int rd = extract32(insn, 0, 5);
+    int imm8 = extract32(insn, 13, 8);
+    int is_double = extract32(insn, 22, 2);
+    uint64_t imm;
+    TCGv_i64 tcg_res;
+
+    if (is_double > 1) {
+        unallocated_encoding(s);
+        return;
+    }
+
+    /* The imm8 encodes the sign bit, enough bits to represent
+     * an exponent in the range 01....1xx to 10....0xx,
+     * and the most significant 4 bits of the mantissa; see
+     * VFPExpandImm() in the v8 ARM ARM.
+     */
+    if (is_double) {
+        imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
+            (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
+            extract32(imm8, 0, 6);
+        imm <<= 48;
+    } else {
+        imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
+            (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
+            (extract32(imm8, 0, 6) << 3);
+        imm <<= 16;
+    }
+
+    tcg_res = tcg_const_i64(imm);
+    write_fp_dreg(s, rd, tcg_res);
+    tcg_temp_free_i64(tcg_res);
 }
 
 /* C3.6.29 Floating point <-> fixed point conversions
-- 
1.8.5

  parent reply	other threads:[~2013-12-30 16:57 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-30 16:34 [Qemu-devel] [PATCH v2 00/10] A64 decoder patchset 5: most floating point Peter Maydell
2013-12-30 16:34 ` [Qemu-devel] [PATCH v2 01/10] target-arm: A64: Add support for dumping AArch64 VFP register state Peter Maydell
2013-12-30 17:57   ` Richard Henderson
2013-12-30 16:34 ` [Qemu-devel] [PATCH v2 02/10] target-arm: A64: Fix vector register access on bigendian hosts Peter Maydell
2013-12-30 17:59   ` Richard Henderson
2013-12-30 16:34 ` [Qemu-devel] [PATCH v2 03/10] target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum Peter Maydell
2013-12-30 16:34 ` [Qemu-devel] [PATCH v2 04/10] target-arm: A64: Add "Floating-point data-processing (2 source)" insns Peter Maydell
2013-12-30 16:34 ` [Qemu-devel] [PATCH v2 05/10] target-arm: A64: Add "Floating-point data-processing (3 " Peter Maydell
2013-12-30 16:34 ` Peter Maydell [this message]
2013-12-30 16:34 ` [Qemu-devel] [PATCH v2 07/10] target-arm: A64: Add support for floating point compare Peter Maydell
2013-12-30 16:34 ` [Qemu-devel] [PATCH v2 08/10] target-arm: A64: Add support for floating point conditional compare Peter Maydell
2013-12-30 16:34 ` [Qemu-devel] [PATCH v2 09/10] target-arm: A64: Add support for floating point cond select Peter Maydell
2013-12-30 16:34 ` [Qemu-devel] [PATCH v2 10/10] target-arm: Give the FPSCR rounding modes names Peter Maydell

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