From: Tom Musta <tommusta@gmail.com>
To: qemu-devel@nongnu.org
Cc: Tom Musta <tommusta@gmail.com>, qemu-ppc@nongnu.org
Subject: [Qemu-devel] [V5 PATCH 15/22] target-ppc: Add VSX ISA2.06 xtsqrt Instructions
Date: Thu, 2 Jan 2014 16:21:28 -0600 [thread overview]
Message-ID: <1388701295-29855-16-git-send-email-tommusta@gmail.com> (raw)
In-Reply-To: <1388701295-29855-1-git-send-email-tommusta@gmail.com>
This patch adds the VSX floating point test for software square
root instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp,
xvtsqrtdp, xvtsqrtsp.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <address@hidden>
---
V2: (a) using locally implemented ppc_float*_get_unbiased_exp
routines (b) eliminated dependency on float*_is_denormal().
target-ppc/fpu_helper.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++
target-ppc/helper.h | 3 ++
target-ppc/translate.c | 6 +++++
3 files changed, 63 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index ee03942..73227b7 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2095,3 +2095,57 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
VSX_TDIV(xstdivdp, 1, float64, f64, -1022, 1023, 52)
VSX_TDIV(xvtdivdp, 2, float64, f64, -1022, 1023, 52)
VSX_TDIV(xvtdivsp, 4, float32, f32, -126, 127, 23)
+
+/* VSX_TSQRT - VSX floating point test for square root
+ * op - instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * tp - type (float32 or float64)
+ * fld - vsr_t field (f32 or f64)
+ * emin - minimum unbiased exponent
+ * emax - maximum unbiased exponent
+ * nbits - number of fraction bits
+ */
+#define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xa, xb; \
+ int i; \
+ int fe_flag = 0; \
+ int fg_flag = 0; \
+ \
+ getVSR(xA(opcode), &xa, env); \
+ getVSR(xB(opcode), &xb, env); \
+ \
+ for (i = 0; i < nels; i++) { \
+ if (unlikely(tp##_is_infinity(xb.fld[i]) || \
+ tp##_is_zero(xb.fld[i]))) { \
+ fe_flag = 1; \
+ fg_flag = 1; \
+ } else { \
+ int e_b = ppc_##tp##_get_unbiased_exp(xb.fld[i]); \
+ \
+ if (unlikely(tp##_is_any_nan(xb.fld[i]))) { \
+ fe_flag = 1; \
+ } else if (unlikely(tp##_is_zero(xb.fld[i]))) { \
+ fe_flag = 1; \
+ } else if (unlikely(tp##_is_neg(xb.fld[i]))) { \
+ fe_flag = 1; \
+ } else if (!tp##_is_zero(xb.fld[i]) && \
+ (e_b <= (emin+nbits))) { \
+ fe_flag = 1; \
+ } \
+ \
+ if (unlikely(tp##_is_zero_or_denormal(xb.fld[i]))) { \
+ /* XB is not zero because of the above check and */ \
+ /* therefore must be denormalized. */ \
+ fg_flag = 1; \
+ } \
+ } \
+ } \
+ \
+ env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
+}
+
+VSX_TSQRT(xstsqrtdp, 1, float64, f64, -1022, 52)
+VSX_TSQRT(xvtsqrtdp, 2, float64, f64, -1022, 52)
+VSX_TSQRT(xvtsqrtsp, 4, float32, f32, -126, 23)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 80cffc9..c413c98 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -259,6 +259,7 @@ DEF_HELPER_2(xsredp, void, env, i32)
DEF_HELPER_2(xssqrtdp, void, env, i32)
DEF_HELPER_2(xsrsqrtedp, void, env, i32)
DEF_HELPER_2(xstdivdp, void, env, i32)
+DEF_HELPER_2(xstsqrtdp, void, env, i32)
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
@@ -268,6 +269,7 @@ DEF_HELPER_2(xvredp, void, env, i32)
DEF_HELPER_2(xvsqrtdp, void, env, i32)
DEF_HELPER_2(xvrsqrtedp, void, env, i32)
DEF_HELPER_2(xvtdivdp, void, env, i32)
+DEF_HELPER_2(xvtsqrtdp, void, env, i32)
DEF_HELPER_2(xvaddsp, void, env, i32)
DEF_HELPER_2(xvsubsp, void, env, i32)
@@ -277,6 +279,7 @@ DEF_HELPER_2(xvresp, void, env, i32)
DEF_HELPER_2(xvsqrtsp, void, env, i32)
DEF_HELPER_2(xvrsqrtesp, void, env, i32)
DEF_HELPER_2(xvtdivsp, void, env, i32)
+DEF_HELPER_2(xvtsqrtsp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ae123c5..3d99bc7 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7312,6 +7312,7 @@ GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -7321,6 +7322,7 @@ GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
@@ -7330,6 +7332,7 @@ GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
#define VSX_LOGICAL(name, tcg_op) \
static void glue(gen_, name)(DisasContext * ctx) \
@@ -10020,6 +10023,7 @@ GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
+GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
@@ -10029,6 +10033,7 @@ GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
+GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
@@ -10038,6 +10043,7 @@ GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
+GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
#undef VSX_LOGICAL
#define VSX_LOGICAL(name, opc2, opc3, fl2) \
--
1.7.1
next prev parent reply other threads:[~2014-01-02 22:22 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-02 22:21 [Qemu-devel] [V5 PATCH 00/22] target-ppc: PowerPC VSX Stage 3 Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 01/22] softfloat: Fix float64_to_uint64 Tom Musta
2014-01-06 12:54 ` Peter Maydell
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 02/22] softfloat: Add float32_to_uint64() Tom Musta
2014-01-06 12:54 ` Peter Maydell
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 03/22] softfloat: Fix float64_to_uint64_round_to_zero Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 04/22] softfloat: Fix float64_to_uint32 Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 05/22] softfloat: Fix float64_to_uint32_round_to_zero Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 06/22] target-ppc: Add set_fprf Argument to fload_invalid_op_excp() Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 07/22] target-ppc: General Support for VSX Helpers Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 08/22] target-ppc: Add VSX ISA2.06 xadd/xsub Instructions Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 09/22] target-ppc: Add VSX ISA2.06 xmul Instructions Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 10/22] target-ppc: Add VSX ISA2.06 xdiv Instructions Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 11/22] target-ppc: Add VSX ISA2.06 xre Instructions Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 12/22] target-ppc: Add VSX ISA2.06 xsqrt Instructions Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 13/22] target-ppc: Add VSX ISA2.06 xrsqrte Instructions Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 14/22] target-ppc: Add VSX ISA2.06 xtdiv Instructions Tom Musta
2014-01-02 22:21 ` Tom Musta [this message]
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 16/22] target-ppc: Add VSX ISA2.06 Multiply Add Instructions Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 17/22] target-ppc: Add VSX xscmp*dp Instructions Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 18/22] target-ppc: Add VSX xmax/xmin Instructions Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 19/22] target-ppc: Add VSX Vector Compare Instructions Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 20/22] target-ppc: Add VSX Floating Point to Floating Point Conversion Instructions Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 21/22] target-ppc: Add VSX ISA2.06 Integer " Tom Musta
2014-01-02 22:21 ` [Qemu-devel] [V5 PATCH 22/22] target-ppc: Add VSX Rounding Instructions Tom Musta
2014-01-27 15:40 ` [Qemu-devel] [Qemu-ppc] [V5 PATCH 00/22] target-ppc: PowerPC VSX Stage 3 Alexander Graf
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