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From: Peter Maydell <peter.maydell@linaro.org>
To: Anthony Liguori <aliguori@amazon.com>
Cc: Blue Swirl <blauwirbel@gmail.com>,
	qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL 11/52] target-arm: Pull "add one cpreg to hashtable" into its own function
Date: Mon,  6 Jan 2014 11:30:16 +0000	[thread overview]
Message-ID: <1389007857-14649-12-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1389007857-14649-1-git-send-email-peter.maydell@linaro.org>

define_one_arm_cp_reg_with_opaque() has a set of nested loops which
insert a cpreg entry into the hashtable for each of the possible
opc/crn/crm values allowed by wildcard specifications. We're about
to add an extra loop to this nesting, so pull the core of the loop
(which adds a single entry to the hashtable) out into its own
function for clarity.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
 target-arm/helper.c | 94 +++++++++++++++++++++++++++++------------------------
 1 file changed, 52 insertions(+), 42 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6ebd7dc..d833163 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1937,6 +1937,57 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
     return cpu_list;
 }
 
+static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+                                   void *opaque, int crm, int opc1, int opc2)
+{
+    /* Private utility function for define_one_arm_cp_reg_with_opaque():
+     * add a single reginfo struct to the hash table.
+     */
+    uint32_t *key = g_new(uint32_t, 1);
+    ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
+    int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
+    *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
+    if (opaque) {
+        r2->opaque = opaque;
+    }
+    /* Make sure reginfo passed to helpers for wildcarded regs
+     * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
+     */
+    r2->crm = crm;
+    r2->opc1 = opc1;
+    r2->opc2 = opc2;
+    /* By convention, for wildcarded registers only the first
+     * entry is used for migration; the others are marked as
+     * NO_MIGRATE so we don't try to transfer the register
+     * multiple times. Special registers (ie NOP/WFI) are
+     * never migratable.
+     */
+    if ((r->type & ARM_CP_SPECIAL) ||
+        ((r->crm == CP_ANY) && crm != 0) ||
+        ((r->opc1 == CP_ANY) && opc1 != 0) ||
+        ((r->opc2 == CP_ANY) && opc2 != 0)) {
+        r2->type |= ARM_CP_NO_MIGRATE;
+    }
+
+    /* Overriding of an existing definition must be explicitly
+     * requested.
+     */
+    if (!(r->type & ARM_CP_OVERRIDE)) {
+        ARMCPRegInfo *oldreg;
+        oldreg = g_hash_table_lookup(cpu->cp_regs, key);
+        if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
+            fprintf(stderr, "Register redefined: cp=%d %d bit "
+                    "crn=%d crm=%d opc1=%d opc2=%d, "
+                    "was %s, now %s\n", r2->cp, 32 + 32 * is64,
+                    r2->crn, r2->crm, r2->opc1, r2->opc2,
+                    oldreg->name, r2->name);
+            g_assert_not_reached();
+        }
+    }
+    g_hash_table_insert(cpu->cp_regs, key, r2);
+}
+
+
 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                                        const ARMCPRegInfo *r, void *opaque)
 {
@@ -1977,48 +2028,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
     for (crm = crmmin; crm <= crmmax; crm++) {
         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
-                uint32_t *key = g_new(uint32_t, 1);
-                ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
-                int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
-                *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
-                if (opaque) {
-                    r2->opaque = opaque;
-                }
-                /* Make sure reginfo passed to helpers for wildcarded regs
-                 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
-                 */
-                r2->crm = crm;
-                r2->opc1 = opc1;
-                r2->opc2 = opc2;
-                /* By convention, for wildcarded registers only the first
-                 * entry is used for migration; the others are marked as
-                 * NO_MIGRATE so we don't try to transfer the register
-                 * multiple times. Special registers (ie NOP/WFI) are
-                 * never migratable.
-                 */
-                if ((r->type & ARM_CP_SPECIAL) ||
-                    ((r->crm == CP_ANY) && crm != 0) ||
-                    ((r->opc1 == CP_ANY) && opc1 != 0) ||
-                    ((r->opc2 == CP_ANY) && opc2 != 0)) {
-                    r2->type |= ARM_CP_NO_MIGRATE;
-                }
-
-                /* Overriding of an existing definition must be explicitly
-                 * requested.
-                 */
-                if (!(r->type & ARM_CP_OVERRIDE)) {
-                    ARMCPRegInfo *oldreg;
-                    oldreg = g_hash_table_lookup(cpu->cp_regs, key);
-                    if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
-                        fprintf(stderr, "Register redefined: cp=%d %d bit "
-                                "crn=%d crm=%d opc1=%d opc2=%d, "
-                                "was %s, now %s\n", r2->cp, 32 + 32 * is64,
-                                r2->crn, r2->crm, r2->opc1, r2->opc2,
-                                oldreg->name, r2->name);
-                        g_assert_not_reached();
-                    }
-                }
-                g_hash_table_insert(cpu->cp_regs, key, r2);
+                add_cpreg_to_hashtable(cpu, r, opaque, crm, opc1, opc2);
             }
         }
     }
-- 
1.8.5

  parent reply	other threads:[~2014-01-06 11:31 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-01-06 11:30 [Qemu-devel] [PULL 00/52] target-arm queue Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 01/52] target-arm: A64: add support for ld/st pair Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 02/52] target-arm: A64: add support for ld/st unsigned imm Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 03/52] target-arm: A64: add support for ld/st with reg offset Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 04/52] target-arm: A64: add support for ld/st with index Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 05/52] target-arm: A64: add support for add, addi, sub, subi Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 06/52] target-arm: A64: add support for move wide instructions Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 07/52] target-arm: A64: add support for 3 src data proc insns Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 08/52] target-arm: A64: implement SVC, BRK Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 09/52] target-arm: A64: Add decoder skeleton for FP instructions Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 10/52] target-arm: A64: implement FMOV Peter Maydell
2014-01-06 11:30 ` Peter Maydell [this message]
2014-01-06 11:30 ` [Qemu-devel] [PULL 12/52] target-arm: Update generic cpreg code for AArch64 Peter Maydell
2014-01-07 19:14   ` Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 13/52] target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 14/52] target-arm: A64: Implement MRS/MSR/SYS/SYSL Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 15/52] target-arm: A64: Implement minimal set of EL0-visible sysregs Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 16/52] target-arm: Widen thread-local register state fields to 64 bits Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 17/52] target-arm: A64: add support for add/sub with carry Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 18/52] target-arm: A64: add support for conditional compare insns Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 19/52] target-arm: aarch64: add support for ld lit Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 20/52] target-arm: Widen exclusive-access support struct fields to 64 bits Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 21/52] target-arm: A64: support for ld/st/cl exclusive Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 22/52] linux-user: AArch64: define TARGET_CLONE_BACKWARDS Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 23/52] linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 24/52] .travis.yml: Add aarch64-* targets Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 25/52] default-configs: Add config for aarch64-linux-user Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 26/52] target-arm: A64: Add support for dumping AArch64 VFP register state Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 27/52] target-arm: A64: Fix vector register access on bigendian hosts Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 28/52] target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 29/52] target-arm: A64: Add "Floating-point data-processing (2 source)" insns Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 30/52] target-arm: A64: Add "Floating-point data-processing (3 " Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 31/52] target-arm: A64: Add fmov (scalar, immediate) instruction Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 32/52] target-arm: A64: Add support for floating point compare Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 33/52] target-arm: A64: Add support for floating point conditional compare Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 34/52] target-arm: A64: Add support for floating point cond select Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 35/52] target-arm: Give the FPSCR rounding modes names Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 36/52] char/cadence_uart: Mark struct fields as public/private Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 37/52] char/cadence_uart: Add missing uart_update_state Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 38/52] char/cadence_uart: Fix reset Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 39/52] char/cadence_uart: s/r_fifo/rx_fifo Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 40/52] char/cadence_uart: Simplify status generation Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 41/52] char/cadence_uart: Define Missing SR/ISR fields Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 42/52] char/cadence_uart: Remove TX timer & add TX FIFO state Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 43/52] char/cadence_uart: Fix can_receive logic Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 44/52] char/cadence_uart: Use the TX fifo for transmission Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 45/52] char/cadence_uart: Delete redundant rx rst logic Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 46/52] char/cadence_uart: Implement Tx flow control Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 47/52] target-arm: use c13_context field for CONTEXTIDR Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 48/52] target-arm: remove raw_read|write duplication Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 49/52] arm/xilinx_zynq: Always instantiate the GEMs Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 50/52] target-arm: fix build with gcc 4.8.2 Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 51/52] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 52/52] hw: arm_gic: Introduce gic_set_priority function Peter Maydell
2014-01-07 19:17 ` [Qemu-devel] [PULL 00/52] target-arm queue Peter Maydell

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