From: Peter Maydell <peter.maydell@linaro.org>
To: Anthony Liguori <aliguori@amazon.com>
Cc: Blue Swirl <blauwirbel@gmail.com>,
qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL 34/52] target-arm: A64: Add support for floating point cond select
Date: Mon, 6 Jan 2014 11:30:39 +0000 [thread overview]
Message-ID: <1389007857-14649-35-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1389007857-14649-1-git-send-email-peter.maydell@linaro.org>
From: Claudio Fontana <claudio.fontana@linaro.org>
This adds decoding support for C3.6.24 FP conditional select.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-arm/translate-a64.c | 45 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 44d8a09..c9fbf0f 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3304,6 +3304,20 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
}
}
+/* copy src FP register to dst FP register; type specifies single or double */
+static void gen_mov_fp2fp(DisasContext *s, int type, int dst, int src)
+{
+ if (type) {
+ TCGv_i64 v = read_fp_dreg(s, src);
+ write_fp_dreg(s, dst, v);
+ tcg_temp_free_i64(v);
+ } else {
+ TCGv_i32 v = read_fp_sreg(s, src);
+ write_fp_sreg(s, dst, v);
+ tcg_temp_free_i32(v);
+ }
+}
+
/* C3.6.24 Floating point conditional select
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+------+-----+------+------+
@@ -3312,7 +3326,36 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
*/
static void disas_fp_csel(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ unsigned int mos, type, rm, cond, rn, rd;
+ int label_continue = -1;
+
+ mos = extract32(insn, 29, 3);
+ type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
+ rm = extract32(insn, 16, 5);
+ cond = extract32(insn, 12, 4);
+ rn = extract32(insn, 5, 5);
+ rd = extract32(insn, 0, 5);
+
+ if (mos || type > 1) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ if (cond < 0x0e) { /* not always */
+ int label_match = gen_new_label();
+ label_continue = gen_new_label();
+ arm_gen_test_cc(cond, label_match);
+ /* nomatch: */
+ gen_mov_fp2fp(s, type, rd, rm);
+ tcg_gen_br(label_continue);
+ gen_set_label(label_match);
+ }
+
+ gen_mov_fp2fp(s, type, rd, rn);
+
+ if (cond < 0x0e) { /* continue */
+ gen_set_label(label_continue);
+ }
}
/* C3.6.25 Floating point data-processing (1 source)
--
1.8.5
next prev parent reply other threads:[~2014-01-06 11:31 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-06 11:30 [Qemu-devel] [PULL 00/52] target-arm queue Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 01/52] target-arm: A64: add support for ld/st pair Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 02/52] target-arm: A64: add support for ld/st unsigned imm Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 03/52] target-arm: A64: add support for ld/st with reg offset Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 04/52] target-arm: A64: add support for ld/st with index Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 05/52] target-arm: A64: add support for add, addi, sub, subi Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 06/52] target-arm: A64: add support for move wide instructions Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 07/52] target-arm: A64: add support for 3 src data proc insns Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 08/52] target-arm: A64: implement SVC, BRK Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 09/52] target-arm: A64: Add decoder skeleton for FP instructions Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 10/52] target-arm: A64: implement FMOV Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 11/52] target-arm: Pull "add one cpreg to hashtable" into its own function Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 12/52] target-arm: Update generic cpreg code for AArch64 Peter Maydell
2014-01-07 19:14 ` Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 13/52] target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 14/52] target-arm: A64: Implement MRS/MSR/SYS/SYSL Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 15/52] target-arm: A64: Implement minimal set of EL0-visible sysregs Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 16/52] target-arm: Widen thread-local register state fields to 64 bits Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 17/52] target-arm: A64: add support for add/sub with carry Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 18/52] target-arm: A64: add support for conditional compare insns Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 19/52] target-arm: aarch64: add support for ld lit Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 20/52] target-arm: Widen exclusive-access support struct fields to 64 bits Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 21/52] target-arm: A64: support for ld/st/cl exclusive Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 22/52] linux-user: AArch64: define TARGET_CLONE_BACKWARDS Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 23/52] linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 24/52] .travis.yml: Add aarch64-* targets Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 25/52] default-configs: Add config for aarch64-linux-user Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 26/52] target-arm: A64: Add support for dumping AArch64 VFP register state Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 27/52] target-arm: A64: Fix vector register access on bigendian hosts Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 28/52] target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 29/52] target-arm: A64: Add "Floating-point data-processing (2 source)" insns Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 30/52] target-arm: A64: Add "Floating-point data-processing (3 " Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 31/52] target-arm: A64: Add fmov (scalar, immediate) instruction Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 32/52] target-arm: A64: Add support for floating point compare Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 33/52] target-arm: A64: Add support for floating point conditional compare Peter Maydell
2014-01-06 11:30 ` Peter Maydell [this message]
2014-01-06 11:30 ` [Qemu-devel] [PULL 35/52] target-arm: Give the FPSCR rounding modes names Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 36/52] char/cadence_uart: Mark struct fields as public/private Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 37/52] char/cadence_uart: Add missing uart_update_state Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 38/52] char/cadence_uart: Fix reset Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 39/52] char/cadence_uart: s/r_fifo/rx_fifo Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 40/52] char/cadence_uart: Simplify status generation Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 41/52] char/cadence_uart: Define Missing SR/ISR fields Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 42/52] char/cadence_uart: Remove TX timer & add TX FIFO state Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 43/52] char/cadence_uart: Fix can_receive logic Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 44/52] char/cadence_uart: Use the TX fifo for transmission Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 45/52] char/cadence_uart: Delete redundant rx rst logic Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 46/52] char/cadence_uart: Implement Tx flow control Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 47/52] target-arm: use c13_context field for CONTEXTIDR Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 48/52] target-arm: remove raw_read|write duplication Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 49/52] arm/xilinx_zynq: Always instantiate the GEMs Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 50/52] target-arm: fix build with gcc 4.8.2 Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 51/52] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 52/52] hw: arm_gic: Introduce gic_set_priority function Peter Maydell
2014-01-07 19:17 ` [Qemu-devel] [PULL 00/52] target-arm queue Peter Maydell
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