From: Peter Maydell <peter.maydell@linaro.org>
To: Anthony Liguori <aliguori@amazon.com>
Cc: Blue Swirl <blauwirbel@gmail.com>,
qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL 07/52] target-arm: A64: add support for 3 src data proc insns
Date: Mon, 6 Jan 2014 11:30:12 +0000 [thread overview]
Message-ID: <1389007857-14649-8-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1389007857-14649-1-git-send-email-peter.maydell@linaro.org>
From: Alexander Graf <agraf@suse.de>
This patch adds emulation for the "Data-processing (3 source)"
family of instructions, namely MADD, MSUB, SMADDL, SMSUBL, SMULH,
UMADDL, UMSUBL, UMULH.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-arm/translate-a64.c | 97 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 95 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index dbc865a..3a9ffdf 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -2128,10 +2128,103 @@ static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_result);
}
-/* Data-processing (3 source) */
+/* C3.5.9 Data-processing (3 source)
+
+ 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
+ +--+------+-----------+------+------+----+------+------+------+
+ |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
+ +--+------+-----------+------+------+----+------+------+------+
+
+ */
static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ int rd = extract32(insn, 0, 5);
+ int rn = extract32(insn, 5, 5);
+ int ra = extract32(insn, 10, 5);
+ int rm = extract32(insn, 16, 5);
+ int op_id = (extract32(insn, 29, 3) << 4) |
+ (extract32(insn, 21, 3) << 1) |
+ extract32(insn, 15, 1);
+ bool sf = extract32(insn, 31, 1);
+ bool is_sub = extract32(op_id, 0, 1);
+ bool is_high = extract32(op_id, 2, 1);
+ bool is_signed = false;
+ TCGv_i64 tcg_op1;
+ TCGv_i64 tcg_op2;
+ TCGv_i64 tcg_tmp;
+
+ /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
+ switch (op_id) {
+ case 0x42: /* SMADDL */
+ case 0x43: /* SMSUBL */
+ case 0x44: /* SMULH */
+ is_signed = true;
+ break;
+ case 0x0: /* MADD (32bit) */
+ case 0x1: /* MSUB (32bit) */
+ case 0x40: /* MADD (64bit) */
+ case 0x41: /* MSUB (64bit) */
+ case 0x4a: /* UMADDL */
+ case 0x4b: /* UMSUBL */
+ case 0x4c: /* UMULH */
+ break;
+ default:
+ unallocated_encoding(s);
+ return;
+ }
+
+ if (is_high) {
+ TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */
+ TCGv_i64 tcg_rd = cpu_reg(s, rd);
+ TCGv_i64 tcg_rn = cpu_reg(s, rn);
+ TCGv_i64 tcg_rm = cpu_reg(s, rm);
+
+ if (is_signed) {
+ tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
+ } else {
+ tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
+ }
+
+ tcg_temp_free_i64(low_bits);
+ return;
+ }
+
+ tcg_op1 = tcg_temp_new_i64();
+ tcg_op2 = tcg_temp_new_i64();
+ tcg_tmp = tcg_temp_new_i64();
+
+ if (op_id < 0x42) {
+ tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn));
+ tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm));
+ } else {
+ if (is_signed) {
+ tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn));
+ tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm));
+ } else {
+ tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn));
+ tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm));
+ }
+ }
+
+ if (ra == 31 && !is_sub) {
+ /* Special-case MADD with rA == XZR; it is the standard MUL alias */
+ tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2);
+ } else {
+ tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2);
+ if (is_sub) {
+ tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
+ } else {
+ tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
+ }
+ }
+
+ if (!sf) {
+ tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd));
+ }
+
+ tcg_temp_free_i64(tcg_op1);
+ tcg_temp_free_i64(tcg_op2);
+ tcg_temp_free_i64(tcg_tmp);
}
/* Add/subtract (with carry) */
--
1.8.5
next prev parent reply other threads:[~2014-01-06 11:31 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-06 11:30 [Qemu-devel] [PULL 00/52] target-arm queue Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 01/52] target-arm: A64: add support for ld/st pair Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 02/52] target-arm: A64: add support for ld/st unsigned imm Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 03/52] target-arm: A64: add support for ld/st with reg offset Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 04/52] target-arm: A64: add support for ld/st with index Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 05/52] target-arm: A64: add support for add, addi, sub, subi Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 06/52] target-arm: A64: add support for move wide instructions Peter Maydell
2014-01-06 11:30 ` Peter Maydell [this message]
2014-01-06 11:30 ` [Qemu-devel] [PULL 08/52] target-arm: A64: implement SVC, BRK Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 09/52] target-arm: A64: Add decoder skeleton for FP instructions Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 10/52] target-arm: A64: implement FMOV Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 11/52] target-arm: Pull "add one cpreg to hashtable" into its own function Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 12/52] target-arm: Update generic cpreg code for AArch64 Peter Maydell
2014-01-07 19:14 ` Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 13/52] target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 14/52] target-arm: A64: Implement MRS/MSR/SYS/SYSL Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 15/52] target-arm: A64: Implement minimal set of EL0-visible sysregs Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 16/52] target-arm: Widen thread-local register state fields to 64 bits Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 17/52] target-arm: A64: add support for add/sub with carry Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 18/52] target-arm: A64: add support for conditional compare insns Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 19/52] target-arm: aarch64: add support for ld lit Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 20/52] target-arm: Widen exclusive-access support struct fields to 64 bits Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 21/52] target-arm: A64: support for ld/st/cl exclusive Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 22/52] linux-user: AArch64: define TARGET_CLONE_BACKWARDS Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 23/52] linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 24/52] .travis.yml: Add aarch64-* targets Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 25/52] default-configs: Add config for aarch64-linux-user Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 26/52] target-arm: A64: Add support for dumping AArch64 VFP register state Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 27/52] target-arm: A64: Fix vector register access on bigendian hosts Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 28/52] target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 29/52] target-arm: A64: Add "Floating-point data-processing (2 source)" insns Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 30/52] target-arm: A64: Add "Floating-point data-processing (3 " Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 31/52] target-arm: A64: Add fmov (scalar, immediate) instruction Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 32/52] target-arm: A64: Add support for floating point compare Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 33/52] target-arm: A64: Add support for floating point conditional compare Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 34/52] target-arm: A64: Add support for floating point cond select Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 35/52] target-arm: Give the FPSCR rounding modes names Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 36/52] char/cadence_uart: Mark struct fields as public/private Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 37/52] char/cadence_uart: Add missing uart_update_state Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 38/52] char/cadence_uart: Fix reset Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 39/52] char/cadence_uart: s/r_fifo/rx_fifo Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 40/52] char/cadence_uart: Simplify status generation Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 41/52] char/cadence_uart: Define Missing SR/ISR fields Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 42/52] char/cadence_uart: Remove TX timer & add TX FIFO state Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 43/52] char/cadence_uart: Fix can_receive logic Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 44/52] char/cadence_uart: Use the TX fifo for transmission Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 45/52] char/cadence_uart: Delete redundant rx rst logic Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 46/52] char/cadence_uart: Implement Tx flow control Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 47/52] target-arm: use c13_context field for CONTEXTIDR Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 48/52] target-arm: remove raw_read|write duplication Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 49/52] arm/xilinx_zynq: Always instantiate the GEMs Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 50/52] target-arm: fix build with gcc 4.8.2 Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 51/52] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER Peter Maydell
2014-01-06 11:30 ` [Qemu-devel] [PULL 52/52] hw: arm_gic: Introduce gic_set_priority function Peter Maydell
2014-01-07 19:17 ` [Qemu-devel] [PULL 00/52] target-arm queue Peter Maydell
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