From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43253) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W08P2-0000i9-Gn for qemu-devel@nongnu.org; Mon, 06 Jan 2014 06:31:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W08P0-0004WH-M5 for qemu-devel@nongnu.org; Mon, 06 Jan 2014 06:31:27 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:44223) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W08P0-0004QZ-GJ for qemu-devel@nongnu.org; Mon, 06 Jan 2014 06:31:26 -0500 From: Peter Maydell Date: Mon, 6 Jan 2014 11:30:13 +0000 Message-Id: <1389007857-14649-9-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1389007857-14649-1-git-send-email-peter.maydell@linaro.org> References: <1389007857-14649-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 08/52] target-arm: A64: implement SVC, BRK List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Blue Swirl , qemu-devel@nongnu.org, Aurelien Jarno From: Alexander Graf Add decoding for the exception generating instructions, and implement SVC (syscalls) and BRK (software breakpoint). Signed-off-by: Alexander Graf Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/translate-a64.c | 51 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 3a9ffdf..9ca6460 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -808,10 +808,57 @@ static void disas_system(DisasContext *s, uint32_t insn) } } -/* Exception generation */ +/* C3.2.3 Exception generation + * + * 31 24 23 21 20 5 4 2 1 0 + * +-----------------+-----+------------------------+-----+----+ + * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | + * +-----------------------+------------------------+----------+ + */ static void disas_exc(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + int opc = extract32(insn, 21, 3); + int op2_ll = extract32(insn, 0, 5); + + switch (opc) { + case 0: + /* SVC, HVC, SMC; since we don't support the Virtualization + * or TrustZone extensions these all UNDEF except SVC. + */ + if (op2_ll != 1) { + unallocated_encoding(s); + break; + } + gen_exception_insn(s, 0, EXCP_SWI); + break; + case 1: + if (op2_ll != 0) { + unallocated_encoding(s); + break; + } + /* BRK */ + gen_exception_insn(s, 0, EXCP_BKPT); + break; + case 2: + if (op2_ll != 0) { + unallocated_encoding(s); + break; + } + /* HLT */ + unsupported_encoding(s, insn); + break; + case 5: + if (op2_ll < 1 || op2_ll > 3) { + unallocated_encoding(s); + break; + } + /* DCPS1, DCPS2, DCPS3 */ + unsupported_encoding(s, insn); + break; + default: + unallocated_encoding(s); + break; + } } /* C3.2.7 Unconditional branch (register) -- 1.8.5