From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38729) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0ACi-0006bV-HM for qemu-devel@nongnu.org; Mon, 06 Jan 2014 08:26:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W0ACg-0003pB-SV for qemu-devel@nongnu.org; Mon, 06 Jan 2014 08:26:52 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:44401) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0ACg-0003ox-LP for qemu-devel@nongnu.org; Mon, 06 Jan 2014 08:26:50 -0500 From: Peter Maydell Date: Mon, 6 Jan 2014 13:11:19 +0000 Message-Id: <1389013881-15726-23-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1389013881-15726-1-git-send-email-peter.maydell@linaro.org> References: <1389013881-15726-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 22/24] target-arm: A64: Add floating-point<->integer conversion instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Tom Musta , Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson From: Will Newton Add support for the AArch64 floating-point <-> integer conversion instructions to disas_fpintconv. In the process we can rearrange and simplify the detection of unallocated encodings a little. We also correct a typo in the instruction encoding diagram for this instruction group: bit 21 is 1, not 0. Signed-off-by: Will Newton Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index ec8abc7..9b23d37 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -3904,7 +3904,7 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) /* C3.6.30 Floating point <-> integer conversions * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ - * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd | + * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd | * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ */ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) @@ -3917,10 +3917,20 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) bool sbit = extract32(insn, 29, 1); bool sf = extract32(insn, 31, 1); - if (!sbit && (rmode < 2) && (opcode > 5)) { + if (sbit) { + unallocated_encoding(s); + return; + } + + if (opcode > 5) { /* FMOV */ bool itof = opcode & 1; + if (rmode >= 2) { + unallocated_encoding(s); + return; + } + switch (sf << 3 | type << 1 | rmode) { case 0x0: /* 32 bit */ case 0xa: /* 64 bit */ @@ -3935,7 +3945,14 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) handle_fmov(s, rd, rn, type, itof); } else { /* actual FP conversions */ - unsupported_encoding(s, insn); + bool itof = extract32(opcode, 1, 1); + + if (type > 1 || (rmode != 0 && opcode > 1)) { + unallocated_encoding(s); + return; + } + + handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type); } } -- 1.8.5