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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Tom Musta" <tommusta@gmail.com>,
	"Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
	patches@linaro.org, "Michael Matz" <matz@suse.de>,
	"Alexander Graf" <agraf@suse.de>,
	"Claudio Fontana" <claudio.fontana@linaro.org>,
	"Dirk Mueller" <dmueller@suse.de>,
	"Will Newton" <will.newton@linaro.org>,
	"Laurent Desnogues" <laurent.desnogues@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	kvmarm@lists.cs.columbia.edu,
	"Christoffer Dall" <christoffer.dall@linaro.org>,
	"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v2 05/24] softfloat: Fix float64_to_uint64
Date: Mon,  6 Jan 2014 13:11:02 +0000	[thread overview]
Message-ID: <1389013881-15726-6-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1389013881-15726-1-git-send-email-peter.maydell@linaro.org>

From: Tom Musta <tommusta@gmail.com>

The comment preceding the float64_to_uint64 routine suggests that
the implementation is broken.  And this is, indeed, the case.

This patch properly implements the conversion of a 64-bit floating
point number to an unsigned, 64 bit integer.

This contribution can be licensed under either the softfloat-2a or -2b
license.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 fpu/softfloat.c | 101 +++++++++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 93 insertions(+), 8 deletions(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 3170b88..2364513 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -204,6 +204,56 @@ static int64 roundAndPackInt64( flag zSign, uint64_t absZ0, uint64_t absZ1 STATU
 }
 
 /*----------------------------------------------------------------------------
+| Takes the 128-bit fixed-point value formed by concatenating `absZ0' and
+| `absZ1', with binary point between bits 63 and 64 (between the input words),
+| and returns the properly rounded 64-bit unsigned integer corresponding to the
+| input.  Ordinarily, the fixed-point input is simply rounded to an integer,
+| with the inexact exception raised if the input cannot be represented exactly
+| as an integer.  However, if the fixed-point input is too large, the invalid
+| exception is raised and the largest unsigned integer is returned.
+*----------------------------------------------------------------------------*/
+
+static int64 roundAndPackUint64(flag zSign, uint64_t absZ0,
+                                uint64_t absZ1 STATUS_PARAM)
+{
+    int8 roundingMode;
+    flag roundNearestEven, increment;
+
+    roundingMode = STATUS(float_rounding_mode);
+    roundNearestEven = (roundingMode == float_round_nearest_even);
+    increment = ((int64_t)absZ1 < 0);
+    if (!roundNearestEven) {
+        if (roundingMode == float_round_to_zero) {
+            increment = 0;
+        } else if (absZ1) {
+            if (zSign) {
+                increment = (roundingMode == float_round_down) && absZ1;
+            } else {
+                increment = (roundingMode == float_round_up) && absZ1;
+            }
+        }
+    }
+    if (increment) {
+        ++absZ0;
+        if (absZ0 == 0) {
+            float_raise(float_flag_invalid STATUS_VAR);
+            return LIT64(0xFFFFFFFFFFFFFFFF);
+        }
+        absZ0 &= ~(((uint64_t)(absZ1<<1) == 0) & roundNearestEven);
+    }
+
+    if (zSign && absZ0) {
+        float_raise(float_flag_invalid STATUS_VAR);
+        return 0;
+    }
+
+    if (absZ1) {
+        STATUS(float_exception_flags) |= float_flag_inexact;
+    }
+    return absZ0;
+}
+
+/*----------------------------------------------------------------------------
 | Returns the fraction bits of the single-precision floating-point value `a'.
 *----------------------------------------------------------------------------*/
 
@@ -6643,16 +6693,51 @@ uint_fast16_t float64_to_uint16_round_to_zero(float64 a STATUS_PARAM)
     return res;
 }
 
-/* FIXME: This looks broken.  */
-uint64_t float64_to_uint64 (float64 a STATUS_PARAM)
-{
-    int64_t v;
+/*----------------------------------------------------------------------------
+| Returns the result of converting the double-precision floating-point value
+| `a' to the 64-bit unsigned integer format.  The conversion is
+| performed according to the IEC/IEEE Standard for Binary Floating-Point
+| Arithmetic---which means in particular that the conversion is rounded
+| according to the current rounding mode.  If `a' is a NaN, the largest
+| positive integer is returned.  If the conversion overflows, the
+| largest unsigned integer is returned.  If 'a' is negative, the value is
+| rounded and zero is returned; negative values that do not round to zero
+| will raise the inexact exception.
+*----------------------------------------------------------------------------*/
 
-    v = float64_val(int64_to_float64(INT64_MIN STATUS_VAR));
-    v += float64_val(a);
-    v = float64_to_int64(make_float64(v) STATUS_VAR);
+uint64_t float64_to_uint64(float64 a STATUS_PARAM)
+{
+    flag aSign;
+    int_fast16_t aExp, shiftCount;
+    uint64_t aSig, aSigExtra;
+    a = float64_squash_input_denormal(a STATUS_VAR);
 
-    return v - INT64_MIN;
+    aSig = extractFloat64Frac(a);
+    aExp = extractFloat64Exp(a);
+    aSign = extractFloat64Sign(a);
+    if (aSign && (aExp > 1022)) {
+        float_raise(float_flag_invalid STATUS_VAR);
+        if (float64_is_any_nan(a)) {
+            return LIT64(0xFFFFFFFFFFFFFFFF);
+        } else {
+            return 0;
+        }
+    }
+    if (aExp) {
+        aSig |= LIT64(0x0010000000000000);
+    }
+    shiftCount = 0x433 - aExp;
+    if (shiftCount <= 0) {
+        if (0x43E < aExp) {
+            float_raise(float_flag_invalid STATUS_VAR);
+            return LIT64(0xFFFFFFFFFFFFFFFF);
+        }
+        aSigExtra = 0;
+        aSig <<= -shiftCount;
+    } else {
+        shift64ExtraRightJamming(aSig, 0, shiftCount, &aSig, &aSigExtra);
+    }
+    return roundAndPackUint64(aSign, aSig, aSigExtra STATUS_VAR);
 }
 
 uint64_t float64_to_uint64_round_to_zero (float64 a STATUS_PARAM)
-- 
1.8.5

  parent reply	other threads:[~2014-01-06 13:27 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-01-06 13:10 [Qemu-devel] [PATCH v2 00/24] A64 decoder patchset 6: rest of floating point Peter Maydell
2014-01-06 13:10 ` [Qemu-devel] [PATCH v2 01/24] softfloat: Fix exception flag handling for float32_to_float16() Peter Maydell
2014-01-06 18:18   ` Richard Henderson
2014-01-06 13:10 ` [Qemu-devel] [PATCH v2 02/24] softfloat: Add float to 16bit integer conversions Peter Maydell
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 03/24] softfloat: Add 16 bit integer to float conversions Peter Maydell
2014-01-06 18:19   ` Richard Henderson
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 04/24] softfloat: Make the int-to-float functions take exact-width types Peter Maydell
2014-01-06 18:20   ` Richard Henderson
2014-01-06 13:11 ` Peter Maydell [this message]
2014-01-06 18:23   ` [Qemu-devel] [PATCH v2 05/24] softfloat: Fix float64_to_uint64 Richard Henderson
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 06/24] softfloat: Only raise Invalid when conversions to int are out of range Peter Maydell
2014-01-06 18:24   ` Richard Henderson
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 07/24] softfloat: Fix factor 2 error for scalbn on denormal inputs Peter Maydell
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 08/24] softfloat: Add float32_to_uint64() Peter Maydell
2014-01-06 18:25   ` Richard Henderson
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 09/24] softfloat: Fix float64_to_uint64_round_to_zero Peter Maydell
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 10/24] softfloat: Fix float64_to_uint32 Peter Maydell
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 11/24] softfloat: Fix float64_to_uint32_round_to_zero Peter Maydell
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 12/24] softfloat: Provide complete set of accessors for fp state Peter Maydell
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 13/24] softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal Peter Maydell
2014-01-06 18:28   ` Richard Henderson
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 14/24] softfloat: Add float16 <=> float64 conversion functions Peter Maydell
2014-01-06 18:30   ` Richard Henderson
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 15/24] softfloat: Refactor code handling various rounding modes Peter Maydell
2014-01-06 18:34   ` Richard Henderson
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 16/24] softfloat: Add support for ties-away rounding Peter Maydell
2014-01-06 18:36   ` Richard Henderson
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 17/24] target-arm: Prepare VFP_CONV_FIX helpers for A64 uses Peter Maydell
2014-01-06 18:37   ` Richard Henderson
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 18/24] target-arm: Rename A32 VFP conversion helpers Peter Maydell
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 19/24] target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion Peter Maydell
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 20/24] target-arm: A64: Add extra VFP fixed point conversion helpers Peter Maydell
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 21/24] target-arm: A64: Add "Floating-point<->fixed-point" instructions Peter Maydell
2014-01-06 18:44   ` Richard Henderson
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 22/24] target-arm: A64: Add floating-point<->integer conversion instructions Peter Maydell
2014-01-06 18:47   ` Richard Henderson
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 23/24] target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions Peter Maydell
2014-01-06 18:52   ` Richard Henderson
2014-01-06 13:11 ` [Qemu-devel] [PATCH v2 24/24] target-arm: A64: Add support for FCVT between half, single and double Peter Maydell
2014-01-06 18:55   ` Richard Henderson

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