From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53905) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0ZBk-0005HS-CE for qemu-devel@nongnu.org; Tue, 07 Jan 2014 11:07:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W0ZBb-0000go-T6 for qemu-devel@nongnu.org; Tue, 07 Jan 2014 11:07:32 -0500 From: Tom Musta Date: Tue, 7 Jan 2014 10:06:08 -0600 Message-Id: <1389110770-5199-21-git-send-email-tommusta@gmail.com> In-Reply-To: <1389110770-5199-1-git-send-email-tommusta@gmail.com> References: <1389110770-5199-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [V4 PATCH 20/22] target-ppc: Add ISA 2.06 ftsqrt List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Tom Musta , qemu-ppc@nongnu.org This patch adds the Floating Point Test for Square Root instruction which was introduced in Power ISA 2.06. Signed-off-by: Tom Musta --- V4: Using the newly added PPC2_FP_TST_ISA206 flag. Modified helper signature per Richard Henderson's review. target-ppc/fpu_helper.c | 31 +++++++++++++++++++++++++++++++ target-ppc/helper.h | 1 + target-ppc/translate.c | 10 ++++++++++ 3 files changed, 42 insertions(+), 0 deletions(-) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index 514a5c9..5a330a2 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1039,6 +1039,37 @@ uint32_t helper_ftdiv(uint64_t fra, uint64_t frb) return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); } +uint32_t helper_ftsqrt(uint64_t frb) +{ + int fe_flag = 0; + int fg_flag = 0; + + if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) { + fe_flag = 1; + fg_flag = 1; + } else { + int e_b = ppc_float64_get_unbiased_exp(frb); + + if (unlikely(float64_is_any_nan(frb))) { + fe_flag = 1; + } else if (unlikely(float64_is_zero(frb))) { + fe_flag = 1; + } else if (unlikely(float64_is_neg(frb))) { + fe_flag = 1; + } else if (!float64_is_zero(frb) && (e_b <= (-1022+52))) { + fe_flag = 1; + } + + if (unlikely(float64_is_zero_or_denormal(frb))) { + /* XB is not zero because of the above check and */ + /* therefore must be denormalized. */ + fg_flag = 1; + } + } + + return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); +} + void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2, uint32_t crfD) { diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 80ad57f..8d5a2ce 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -100,6 +100,7 @@ DEF_HELPER_2(frsqrte, i64, env, i64) DEF_HELPER_4(fsel, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_2(ftdiv, TCG_CALL_NO_RWG_SE, i32, i64, i64) +DEF_HELPER_FLAGS_1(ftsqrt, TCG_CALL_NO_RWG_SE, i32, i64) #define dh_alias_avr ptr #define dh_ctype_avr ppc_avr_t * diff --git a/target-ppc/translate.c b/target-ppc/translate.c index e6cae60..5b2143a 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2248,6 +2248,15 @@ static void gen_ftdiv(DisasContext *ctx) cpu_fpr[rB(ctx->opcode)]); } +static void gen_ftsqrt(DisasContext *ctx) +{ + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); +} + /*** Floating-Point compare ***/ @@ -9772,6 +9781,7 @@ GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206), +GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206), GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), -- 1.7.1