From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0ZBA-0004EQ-Fs for qemu-devel@nongnu.org; Tue, 07 Jan 2014 11:07:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W0ZB2-0000Uv-3C for qemu-devel@nongnu.org; Tue, 07 Jan 2014 11:06:56 -0500 From: Tom Musta Date: Tue, 7 Jan 2014 10:05:54 -0600 Message-Id: <1389110770-5199-7-git-send-email-tommusta@gmail.com> In-Reply-To: <1389110770-5199-1-git-send-email-tommusta@gmail.com> References: <1389110770-5199-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [V4 PATCH 06/22] target-ppc: Add ISA 2.06 divwe[o] Instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Tom Musta , qemu-ppc@nongnu.org This patch addes the signed Divide Word Extended instructions which were introduced in Power ISA 2.06B. Signed-off-by: Tom Musta --- V2: Eliminating extraneous code in the overflow case per comments from Richard Henderson. Fixed corner case bug in divweu (check for (RA) >= (RB)). V4: Using newly added PPC2_DIVE_ISA206 flag. Converted to helper per Richard Henderson's review. target-ppc/helper.h | 1 + target-ppc/int_helper.c | 32 ++++++++++++++++++++++++++++++++ target-ppc/translate.c | 4 ++++ 3 files changed, 37 insertions(+), 0 deletions(-) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 41025c9..ae2e990 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -35,6 +35,7 @@ DEF_HELPER_4(divdeu, i64, env, i64, i64, i32) DEF_HELPER_4(divde, i64, env, i64, i64, i32) #endif DEF_HELPER_4(divweu, tl, env, tl, tl, i32) +DEF_HELPER_4(divwe, tl, env, tl, tl, i32) DEF_HELPER_FLAGS_1(cntlzw, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 45586be..71db3fb 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -72,6 +72,38 @@ target_ulong helper_divweu(CPUPPCState *env, target_ulong ra, target_ulong rb, return (target_ulong)rt; } +target_ulong helper_divwe(CPUPPCState *env, target_ulong ra, target_ulong rb, + uint32_t oe) +{ + int64_t rt = 0; + int overflow = 0; + + int64_t dividend = (int64_t)ra << 32; + int64_t divisor = (int64_t)((int32_t)rb); + + if (unlikely((divisor == 0) || + ((divisor == -1ull) && (dividend == INT64_MIN)))) { + overflow = 1; + } else { + rt = dividend / divisor; + overflow = rt != (int32_t)rt; + } + + if (unlikely(overflow)) { + rt = 0; /* Undefined */ + } + + if (oe) { + if (unlikely(overflow)) { + env->so = env->ov = 1; + } else { + env->ov = 0; + } + } + + return (target_ulong)rt; +} + #if defined(TARGET_PPC64) uint64_t helper_divdeu(CPUPPCState *env, uint64_t ra, uint64_t rb, uint32_t oe) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index a7d3295..d476d92 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1000,6 +1000,8 @@ static void gen_##name(DisasContext *ctx) \ GEN_DIVE(divweu, divweu, 0); GEN_DIVE(divweuo, divweu, 1); +GEN_DIVE(divwe, divwe, 0); +GEN_DIVE(divweo, divwe, 1); #if defined(TARGET_PPC64) static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, @@ -9622,6 +9624,8 @@ GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), +GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), +GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), -- 1.7.1