From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53425) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0ZBC-0004IW-TC for qemu-devel@nongnu.org; Tue, 07 Jan 2014 11:07:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W0ZB4-0000VS-8N for qemu-devel@nongnu.org; Tue, 07 Jan 2014 11:06:58 -0500 From: Tom Musta Date: Tue, 7 Jan 2014 10:05:55 -0600 Message-Id: <1389110770-5199-8-git-send-email-tommusta@gmail.com> In-Reply-To: <1389110770-5199-1-git-send-email-tommusta@gmail.com> References: <1389110770-5199-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [V4 PATCH 07/22] target-ppc: Add Flag for ISA2.06 Atomic Instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Tom Musta , qemu-ppc@nongnu.org This patch adds a flag for the atomic instructions introduced in Power ISA V2.06B. Signed-off-by: Tom Musta --- V4: Split into new and separate patch. Added to Power7+ model. target-ppc/cpu.h | 5 ++++- target-ppc/translate_init.c | 9 ++++++--- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 8ba0d32..3057ac8 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1881,10 +1881,13 @@ enum { PPC2_PERM_ISA206 = 0x0000000000000080ULL, /* ISA 2.06B divide extended variants */ PPC2_DIVE_ISA206 = 0x0000000000000100ULL, + /* ISA 2.06B larx/stcx. instructions */ + PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL, + #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ - PPC2_DIVE_ISA206) + PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206) }; /*****************************************************************************/ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 390024e..5778760 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7237,7 +7237,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206; + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206; pcc->msr_mask = 0x800000000284FF37ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) @@ -7276,7 +7277,8 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data) PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206; + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206; pcc->msr_mask = 0x800000000204FF37ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) @@ -7315,7 +7317,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | - PPC2_PERM_ISA206 | PPC2_DIVE_ISA206; + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206; pcc->msr_mask = 0x800000000284FF36ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) -- 1.7.1