From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35928) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0ctk-0004JD-E6 for qemu-devel@nongnu.org; Tue, 07 Jan 2014 15:05:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W0cti-0003XU-SN for qemu-devel@nongnu.org; Tue, 07 Jan 2014 15:05:12 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:44524) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0cti-0003Am-KZ for qemu-devel@nongnu.org; Tue, 07 Jan 2014 15:05:10 -0500 From: Peter Maydell Date: Tue, 7 Jan 2014 20:03:37 +0000 Message-Id: <1389125052-22931-42-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1389125052-22931-1-git-send-email-peter.maydell@linaro.org> References: <1389125052-22931-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 41/76] char/cadence_uart: Define Missing SR/ISR fields List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Blue Swirl , qemu-devel@nongnu.org, Aurelien Jarno From: Peter Crosthwaite Some (interrupt) status register bits relating to the TxFIFO path were not defined. Define them. This prepares support for proper Tx data path flow control. Signed-off-by: Peter Crosthwaite Message-id: 2068b963f0af8cc834c353944e9fa816d950b163.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index ddd7267..216eed7 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -34,6 +34,9 @@ #define UART_SR_INTR_RFUL 0x00000004 #define UART_SR_INTR_TEMPTY 0x00000008 #define UART_SR_INTR_TFUL 0x00000010 +/* somewhat awkwardly, TTRIG is misaligned between SR and ISR */ +#define UART_SR_TTRIG 0x00002000 +#define UART_INTR_TTRIG 0x00000400 /* bits fields in CSR that correlate to CISR. If any of these bits are set in * SR, then the same bit in CISR is set high too */ #define UART_SR_TO_CISR_MASK 0x0000001F @@ -43,6 +46,7 @@ #define UART_INTR_PARE 0x00000080 #define UART_INTR_TIMEOUT 0x00000100 #define UART_INTR_DMSI 0x00000200 +#define UART_INTR_TOVR 0x00001000 #define UART_SR_RACTIVE 0x00000400 #define UART_SR_TACTIVE 0x00000800 -- 1.8.5