From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35909) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0ctj-0004He-Ro for qemu-devel@nongnu.org; Tue, 07 Jan 2014 15:05:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W0cth-0003Wm-VD for qemu-devel@nongnu.org; Tue, 07 Jan 2014 15:05:11 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:44524) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0cth-0003Am-On for qemu-devel@nongnu.org; Tue, 07 Jan 2014 15:05:09 -0500 From: Peter Maydell Date: Tue, 7 Jan 2014 20:03:42 +0000 Message-Id: <1389125052-22931-47-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1389125052-22931-1-git-send-email-peter.maydell@linaro.org> References: <1389125052-22931-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 46/76] char/cadence_uart: Implement Tx flow control List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Blue Swirl , qemu-devel@nongnu.org, Aurelien Jarno From: Peter Crosthwaite If the UART back-end blocks, buffer in the Tx FIFO to try again later. This stops the IO-thread busy waiting on char back-ends (which causes all sorts of performance problems). Signed-off-by: Peter Crosthwaite Message-id: 4bea048b3ab38425701d82ccc1ab92545c26b79c.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/char/cadence_uart.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 8a9ef81..1012f1a 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -286,6 +286,34 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) uart_update_status(s); } +static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond, + void *opaque) +{ + UartState *s = opaque; + int ret; + + /* instant drain the fifo when there's no back-end */ + if (!s->chr) { + s->tx_count = 0; + } + + if (!s->tx_count) { + return FALSE; + } + + ret = qemu_chr_fe_write(s->chr, s->tx_fifo, s->tx_count); + s->tx_count -= ret; + memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count); + + if (s->tx_count) { + int r = qemu_chr_fe_add_watch(s->chr, G_IO_OUT, cadence_uart_xmit, s); + assert(r); + } + + uart_update_status(s); + return FALSE; +} + static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size) { if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { @@ -306,8 +334,7 @@ static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size) memcpy(s->tx_fifo + s->tx_count, buf, size); s->tx_count += size; - qemu_chr_fe_write_all(s->chr, s->tx_fifo, s->tx_count); - s->tx_count = 0; + cadence_uart_xmit(NULL, G_IO_OUT, s); } static void uart_receive(void *opaque, const uint8_t *buf, int size) -- 1.8.5