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From: Peter Maydell <peter.maydell@linaro.org>
To: Anthony Liguori <aliguori@amazon.com>
Cc: Blue Swirl <blauwirbel@gmail.com>,
	qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL 69/76] target-arm: Prepare VFP_CONV_FIX helpers for A64 uses
Date: Tue,  7 Jan 2014 20:04:05 +0000	[thread overview]
Message-ID: <1389125052-22931-70-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1389125052-22931-1-git-send-email-peter.maydell@linaro.org>

From: Will Newton <will.newton@linaro.org>

Make the VFP_CONV_FIX helpers a little more flexible in
preparation for the A64 uses. This requires two changes:
 * use the correct softfloat conversion function based on itype
   rather than always the int32 one; this is possible now that
   softfloat provides int16 versions and necessary for the
   future conversion-to-int64 A64 variants. This also allows
   us to drop the awkward 'sign' macro argument.
 * split the 'fsz' argument which currently controls both
   width of the input float type and width of the output
   integer type into two; this will allow us to specify the
   A64 64-bit-int-to-single conversion function, where the
   two widths are different.

We can also drop the (itype##_t) cast now that softfloat
guarantees that all the itype##_to_float* functions take
an integer argument of exactly the correct type.

Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
 target-arm/helper.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6f629f3..5579565 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3976,17 +3976,17 @@ float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
 }
 
 /* VFP3 fixed point conversion.  */
-#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
-float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t  x, uint32_t shift, \
-                                    void *fpstp) \
+#define VFP_CONV_FIX(name, p, fsz, isz, itype)                         \
+float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
+                                     void *fpstp) \
 { \
     float_status *fpst = fpstp; \
     float##fsz tmp; \
-    tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
+    tmp = itype##_to_##float##fsz(x, fpst); \
     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
 } \
-uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
-                                       void *fpstp) \
+uint##isz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
+                                      void *fpstp) \
 { \
     float_status *fpst = fpstp; \
     float##fsz tmp; \
@@ -3998,14 +3998,14 @@ uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
     return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
 }
 
-VFP_CONV_FIX(sh, d, 64, int16, )
-VFP_CONV_FIX(sl, d, 64, int32, )
-VFP_CONV_FIX(uh, d, 64, uint16, u)
-VFP_CONV_FIX(ul, d, 64, uint32, u)
-VFP_CONV_FIX(sh, s, 32, int16, )
-VFP_CONV_FIX(sl, s, 32, int32, )
-VFP_CONV_FIX(uh, s, 32, uint16, u)
-VFP_CONV_FIX(ul, s, 32, uint32, u)
+VFP_CONV_FIX(sh, d, 64, 64, int16)
+VFP_CONV_FIX(sl, d, 64, 64, int32)
+VFP_CONV_FIX(uh, d, 64, 64, uint16)
+VFP_CONV_FIX(ul, d, 64, 64, uint32)
+VFP_CONV_FIX(sh, s, 32, 32, int16)
+VFP_CONV_FIX(sl, s, 32, 32, int32)
+VFP_CONV_FIX(uh, s, 32, 32, uint16)
+VFP_CONV_FIX(ul, s, 32, 32, uint32)
 #undef VFP_CONV_FIX
 
 /* Half precision conversions.  */
-- 
1.8.5

  parent reply	other threads:[~2014-01-07 20:05 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-01-07 20:02 [Qemu-devel] [PULL 00/76] target-arm queue Peter Maydell
2014-01-07 20:02 ` [Qemu-devel] [PULL 01/76] target-arm: A64: add support for ld/st pair Peter Maydell
2014-01-07 20:02 ` [Qemu-devel] [PULL 02/76] target-arm: A64: add support for ld/st unsigned imm Peter Maydell
2014-01-07 20:02 ` [Qemu-devel] [PULL 03/76] target-arm: A64: add support for ld/st with reg offset Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 04/76] target-arm: A64: add support for ld/st with index Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 05/76] target-arm: A64: add support for add, addi, sub, subi Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 06/76] target-arm: A64: add support for move wide instructions Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 07/76] target-arm: A64: add support for 3 src data proc insns Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 08/76] target-arm: A64: implement SVC, BRK Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 09/76] target-arm: A64: Add decoder skeleton for FP instructions Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 10/76] target-arm: A64: implement FMOV Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 11/76] target-arm: Pull "add one cpreg to hashtable" into its own function Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 12/76] target-arm: Update generic cpreg code for AArch64 Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 13/76] target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 14/76] target-arm: A64: Implement MRS/MSR/SYS/SYSL Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 15/76] target-arm: A64: Implement minimal set of EL0-visible sysregs Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 16/76] target-arm: Widen thread-local register state fields to 64 bits Peter Maydell
2014-01-08 18:32   ` Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 17/76] target-arm: A64: add support for add/sub with carry Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 18/76] target-arm: A64: add support for conditional compare insns Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 19/76] target-arm: aarch64: add support for ld lit Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 20/76] target-arm: Widen exclusive-access support struct fields to 64 bits Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 21/76] target-arm: A64: support for ld/st/cl exclusive Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 22/76] linux-user: AArch64: define TARGET_CLONE_BACKWARDS Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 23/76] linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 24/76] .travis.yml: Add aarch64-* targets Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 25/76] default-configs: Add config for aarch64-linux-user Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 26/76] target-arm: A64: Add support for dumping AArch64 VFP register state Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 27/76] target-arm: A64: Fix vector register access on bigendian hosts Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 28/76] target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 29/76] target-arm: A64: Add "Floating-point data-processing (2 source)" insns Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 30/76] target-arm: A64: Add "Floating-point data-processing (3 " Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 31/76] target-arm: A64: Add fmov (scalar, immediate) instruction Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 32/76] target-arm: A64: Add support for floating point compare Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 33/76] target-arm: A64: Add support for floating point conditional compare Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 34/76] target-arm: A64: Add support for floating point cond select Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 35/76] target-arm: Give the FPSCR rounding modes names Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 36/76] char/cadence_uart: Mark struct fields as public/private Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 37/76] char/cadence_uart: Add missing uart_update_state Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 38/76] char/cadence_uart: Fix reset Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 39/76] char/cadence_uart: s/r_fifo/rx_fifo Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 40/76] char/cadence_uart: Simplify status generation Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 41/76] char/cadence_uart: Define Missing SR/ISR fields Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 42/76] char/cadence_uart: Remove TX timer & add TX FIFO state Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 43/76] char/cadence_uart: Fix can_receive logic Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 44/76] char/cadence_uart: Use the TX fifo for transmission Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 45/76] char/cadence_uart: Delete redundant rx rst logic Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 46/76] char/cadence_uart: Implement Tx flow control Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 47/76] target-arm: use c13_context field for CONTEXTIDR Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 48/76] target-arm: remove raw_read|write duplication Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 49/76] arm/xilinx_zynq: Always instantiate the GEMs Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 50/76] target-arm: fix build with gcc 4.8.2 Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 51/76] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 52/76] hw: arm_gic: Introduce gic_set_priority function Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 53/76] softfloat: Fix exception flag handling for float32_to_float16() Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 54/76] softfloat: Add float to 16bit integer conversions Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 55/76] softfloat: Add 16 bit integer to float conversions Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 56/76] softfloat: Make the int-to-float functions take exact-width types Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 57/76] softfloat: Fix float64_to_uint64 Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 58/76] softfloat: Only raise Invalid when conversions to int are out of range Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 59/76] softfloat: Fix factor 2 error for scalbn on denormal inputs Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 60/76] softfloat: Add float32_to_uint64() Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 61/76] softfloat: Fix float64_to_uint64_round_to_zero Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 62/76] softfloat: Fix float64_to_uint32 Peter Maydell
2014-01-07 20:03 ` [Qemu-devel] [PULL 63/76] softfloat: Fix float64_to_uint32_round_to_zero Peter Maydell
2014-01-07 20:04 ` [Qemu-devel] [PULL 64/76] softfloat: Provide complete set of accessors for fp state Peter Maydell
2014-01-07 20:04 ` [Qemu-devel] [PULL 65/76] softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal Peter Maydell
2014-01-07 20:04 ` [Qemu-devel] [PULL 66/76] softfloat: Add float16 <=> float64 conversion functions Peter Maydell
2014-01-07 20:04 ` [Qemu-devel] [PULL 67/76] softfloat: Refactor code handling various rounding modes Peter Maydell
2014-01-07 20:04 ` [Qemu-devel] [PULL 68/76] softfloat: Add support for ties-away rounding Peter Maydell
2014-01-07 20:04 ` Peter Maydell [this message]
2014-01-07 20:04 ` [Qemu-devel] [PULL 70/76] target-arm: Rename A32 VFP conversion helpers Peter Maydell
2014-01-07 20:04 ` [Qemu-devel] [PULL 71/76] target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion Peter Maydell
2014-01-07 20:04 ` [Qemu-devel] [PULL 72/76] target-arm: A64: Add extra VFP fixed point conversion helpers Peter Maydell
2014-01-07 20:04 ` [Qemu-devel] [PULL 73/76] target-arm: A64: Add floating-point<->fixed-point instructions Peter Maydell
2014-01-07 20:04 ` [Qemu-devel] [PULL 74/76] target-arm: A64: Add floating-point<->integer conversion instructions Peter Maydell
2014-01-07 20:04 ` [Qemu-devel] [PULL 75/76] target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions Peter Maydell
2014-01-07 20:04 ` [Qemu-devel] [PULL 76/76] target-arm: A64: Add support for FCVT between half, single and double Peter Maydell

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