From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47384) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0dmR-0003CU-T9 for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:01:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W0dmN-0003aE-7Z for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:01:43 -0500 Received: from mail-qc0-x22f.google.com ([2607:f8b0:400d:c01::22f]:62741) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0dmN-0003a4-2D for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:01:39 -0500 Received: by mail-qc0-f175.google.com with SMTP id n7so663579qcx.6 for ; Tue, 07 Jan 2014 13:01:38 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Tue, 7 Jan 2014 13:00:03 -0800 Message-Id: <1389128439-10067-14-git-send-email-rth@twiddle.net> In-Reply-To: <1389128439-10067-1-git-send-email-rth@twiddle.net> References: <1389128439-10067-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 13/49] target-i386: Remove gen_op_st_T1_A0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@amazon.com Propagate its definition into all users. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target-i386/translate.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 725d5ec..a1a23a6 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -586,11 +586,6 @@ static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0) tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE); } -static inline void gen_op_st_T1_A0(DisasContext *s, int idx) -{ - gen_op_st_v(s, idx, cpu_T[1], cpu_A0); -} - static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d) { if (d == OR_TMP0) { @@ -2490,7 +2485,7 @@ static void gen_push_T1(DisasContext *s) gen_op_movq_A0_reg(R_ESP); if (s->dflag) { gen_op_addq_A0_im(-8); - gen_op_st_T1_A0(s, MO_64); + gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0); } else { gen_op_addq_A0_im(-2); gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); @@ -2512,7 +2507,7 @@ static void gen_push_T1(DisasContext *s) gen_op_andl_A0_ffff(); gen_op_addl_A0_seg(s, R_SS); } - gen_op_st_T1_A0(s, s->dflag + 1); + gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0); if (s->ss32 && !s->addseg) gen_op_mov_reg_A0(1, R_ESP); -- 1.8.4.2