From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47421) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0dmW-0003MP-Qu for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:01:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W0dmS-0003bA-3X for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:01:48 -0500 Received: from mail-qc0-x22b.google.com ([2607:f8b0:400d:c01::22b]:36157) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0dmR-0003az-Ty for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:01:44 -0500 Received: by mail-qc0-f171.google.com with SMTP id c9so693542qcz.30 for ; Tue, 07 Jan 2014 13:01:43 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Tue, 7 Jan 2014 13:00:06 -0800 Message-Id: <1389128439-10067-17-git-send-email-rth@twiddle.net> In-Reply-To: <1389128439-10067-1-git-send-email-rth@twiddle.net> References: <1389128439-10067-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 16/49] target-i386: Tidy movsl List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@amazon.com Always perform a sign-extending load. In the extremely unlikely case that we've used an 0x66 prefix, the extension to 64-bits is unnecessary but not wrong; the store will still examine only 16 bits. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target-i386/translate.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index f3baa4d..0a414c4 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7747,11 +7747,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_mov_reg_T0(d_ot, reg); } else { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); - if (d_ot == MO_64) { - gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0); - } else { - gen_op_ld_v(s, MO_32, cpu_T[0], cpu_A0); - } + gen_op_ld_v(s, MO_32 | MO_SIGN, cpu_T[0], cpu_A0); gen_op_mov_reg_T0(d_ot, reg); } } else -- 1.8.4.2