From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47483) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0dmg-0003ee-4A for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:02:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W0dmb-0003cj-CA for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:01:58 -0500 Received: from mail-qc0-x22d.google.com ([2607:f8b0:400d:c01::22d]:40078) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0dma-0003cU-Vy for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:01:53 -0500 Received: by mail-qc0-f173.google.com with SMTP id m20so674848qcx.32 for ; Tue, 07 Jan 2014 13:01:52 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Tue, 7 Jan 2014 13:00:11 -0800 Message-Id: <1389128439-10067-22-git-send-email-rth@twiddle.net> In-Reply-To: <1389128439-10067-1-git-send-email-rth@twiddle.net> References: <1389128439-10067-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 21/49] target-i386: Tidy extend + store List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@amazon.com We can now use tcg_gen_qemu_st_i32 directly to avoid the extension. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target-i386/translate.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 58be71f..ad6ecd3 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -4228,12 +4228,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, xmm_regs[reg].XMM_L(val & 3))); - tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); if (mod == 3) { + tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); gen_op_mov_reg_v(ot, rm, cpu_T[0]); } else { - tcg_gen_qemu_st_tl(cpu_T[0], cpu_A0, - s->mem_index, MO_LEUL); + tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUL); } } else { /* pextrq */ #ifdef TARGET_X86_64 @@ -5970,8 +5970,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, switch(op >> 4) { case 1: gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env); - tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); + tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUL); break; case 2: gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env); @@ -5981,8 +5981,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 3: default: gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env); - tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); + tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUW); break; } gen_helper_fpop(cpu_env); @@ -5991,13 +5991,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, switch(op >> 4) { case 0: gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env); - tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); + tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUL); break; case 1: gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env); - tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); + tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUL); break; case 2: gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env); @@ -6007,8 +6007,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 3: default: gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env); - tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); + tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUW); break; } if ((op & 7) == 3) @@ -6033,8 +6033,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 0x0f: /* fnstcw mem */ gen_helper_fnstcw(cpu_tmp2_i32, cpu_env); - tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); + tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUW); break; case 0x1d: /* fldt mem */ gen_update_cc_op(s); @@ -6059,8 +6059,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 0x2f: /* fnstsw mem */ gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); - tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); + tcg_gen_qemu_st_i32(cpu_tmp2_i32, cpu_A0, + s->mem_index, MO_LEUW); break; case 0x3c: /* fbld */ gen_update_cc_op(s); -- 1.8.4.2