From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47722) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0dn4-0004Mm-4P for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:02:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W0dmz-0003jo-6i for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:02:22 -0500 Received: from mail-qc0-x232.google.com ([2607:f8b0:400d:c01::232]:37589) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0dmz-0003jg-0P for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:02:17 -0500 Received: by mail-qc0-f178.google.com with SMTP id i17so669867qcy.37 for ; Tue, 07 Jan 2014 13:02:16 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Tue, 7 Jan 2014 13:00:26 -0800 Message-Id: <1389128439-10067-37-git-send-email-rth@twiddle.net> In-Reply-To: <1389128439-10067-1-git-send-email-rth@twiddle.net> References: <1389128439-10067-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 36/49] target-i386: Change gen_op_mov_reg_A0 size parameter to TCGMemOp List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@amazon.com Change the domain of the parameter and update all callers. Which lets us defer completely to gen_op_mov_reg_v. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target-i386/translate.c | 32 ++++++++------------------------ 1 file changed, 8 insertions(+), 24 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 8861973..9b191ad 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -334,25 +334,9 @@ static inline void gen_op_mov_reg_T1(TCGMemOp ot, int reg) gen_op_mov_reg_v(ot, reg, cpu_T[1]); } -static void gen_op_mov_reg_A0(TCGMemOp size, int reg) +static inline void gen_op_mov_reg_A0(TCGMemOp size, int reg) { - switch (size) { - case MO_8: - tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16); - break; - case MO_16: - /* For x86_64, this sets the higher half of register to zero. - For i386, this is equivalent to a mov. */ - tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0); - break; -#ifdef TARGET_X86_64 - case MO_32: - tcg_gen_mov_tl(cpu_regs[reg], cpu_A0); - break; -#endif - default: - tcg_abort(); - } + gen_op_mov_reg_v(size, reg, cpu_A0); } static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg) @@ -2381,7 +2365,7 @@ static void gen_push_T0(DisasContext *s) gen_op_addq_A0_im(-2); gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); } - gen_op_mov_reg_A0(2, R_ESP); + gen_op_mov_reg_A0(MO_64, R_ESP); } else #endif { @@ -2402,9 +2386,9 @@ static void gen_push_T0(DisasContext *s) } gen_op_st_v(s, s->dflag + 1, cpu_T[0], cpu_A0); if (s->ss32 && !s->addseg) - gen_op_mov_reg_A0(1, R_ESP); + gen_op_mov_reg_A0(MO_32, R_ESP); else - gen_op_mov_reg_T1(s->ss32 + 1, R_ESP); + gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP); } } @@ -2422,7 +2406,7 @@ static void gen_push_T1(DisasContext *s) gen_op_addq_A0_im(-2); gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0); } - gen_op_mov_reg_A0(2, R_ESP); + gen_op_mov_reg_A0(MO_64, R_ESP); } else #endif { @@ -2442,7 +2426,7 @@ static void gen_push_T1(DisasContext *s) gen_op_st_v(s, s->dflag + 1, cpu_T[1], cpu_A0); if (s->ss32 && !s->addseg) - gen_op_mov_reg_A0(1, R_ESP); + gen_op_mov_reg_A0(MO_32, R_ESP); else gen_stack_update(s, (-2) << s->dflag); } @@ -5566,7 +5550,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, s->addseg = 0; gen_lea_modrm(env, s, modrm); s->addseg = val; - gen_op_mov_reg_A0(ot - MO_16, reg); + gen_op_mov_reg_A0(ot, reg); break; case 0xa0: /* mov EAX, Ov */ -- 1.8.4.2