From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52302) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W1IfO-0000XB-6C for qemu-devel@nongnu.org; Thu, 09 Jan 2014 11:41:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W1IfI-0007FR-2V for qemu-devel@nongnu.org; Thu, 09 Jan 2014 11:41:10 -0500 Received: from mx1.redhat.com ([209.132.183.28]:3208) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W1IfH-0007F5-Oj for qemu-devel@nongnu.org; Thu, 09 Jan 2014 11:41:03 -0500 From: Igor Mammedov Date: Thu, 9 Jan 2014 17:36:35 +0100 Message-Id: <1389285399-28417-6-git-send-email-imammedo@redhat.com> In-Reply-To: <1389285399-28417-1-git-send-email-imammedo@redhat.com> References: <1389285399-28417-1-git-send-email-imammedo@redhat.com> Subject: [Qemu-devel] [PATCH 5/9] pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resources List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: mst@redhat.com, hutao@cn.fujitsu.com, mjt@tls.msk.ru, chen.fan.fnst@cn.fujitsu.com, aliguori@amazon.com, anthony.perard@citrix.com, afaerber@suse.de .. so that they might not be used by PCI devices. Note: Resort to concatenating templates with preprocessor help, because 1.0b spec isn't supporting ConcatenateResTemplate, as result Windows XP fails to execute PCI0._CRS method if ConcatenateResTemplate() is used. Signed-off-by: Igor Mammedov --- Follow up patch will expose them as motherboard resources v2: * add comments about holes origins for PCI/CPU hotplug and GPE0 --- hw/i386/acpi-dsdt-pci-crs.dsl | 8 +------- hw/i386/acpi-dsdt.dsl | 32 ++++++++++++++++++++++++++++++++ hw/i386/q35-acpi-dsdt.dsl | 8 ++++++++ 3 files changed, 41 insertions(+), 7 deletions(-) diff --git a/hw/i386/acpi-dsdt-pci-crs.dsl b/hw/i386/acpi-dsdt-pci-crs.dsl index b375a19..8b631d1 100644 --- a/hw/i386/acpi-dsdt-pci-crs.dsl +++ b/hw/i386/acpi-dsdt-pci-crs.dsl @@ -37,13 +37,7 @@ Scope(\_SB.PCI0) { 0x0000, // Address Translation Offset 0x0CF8, // Address Length ,, , TypeStatic) - WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0D00, // Address Range Minimum - 0xFFFF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0xF300, // Address Length - ,, , TypeStatic) + BOARD_SPECIFIC_PCI_RESOURSES DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Address Space Granularity 0x000A0000, // Address Range Minimum diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl index 3dc4789..f501c8d 100644 --- a/hw/i386/acpi-dsdt.dsl +++ b/hw/i386/acpi-dsdt.dsl @@ -35,6 +35,38 @@ DefinitionBlock ( /**************************************************************** * PCI Bus definition ****************************************************************/ +#define BOARD_SPECIFIC_PCI_RESOURSES \ + WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \ + 0x0000, \ + 0x0D00, \ + 0xADFF, \ + 0x0000, \ + 0xA100, \ + ,, , TypeStatic) \ + /* 0xae00-0xae0e hole for PCI hotplug, hw/acpi/piix4.c:PCI_HOTPLUG_ADDR */ \ + WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \ + 0x0000, \ + 0xAE0F, \ + 0xAEFF, \ + 0x0000, \ + 0x00F1, \ + ,, , TypeStatic) \ + /* 0xaf00-0xaf1f hole for CPU hotplug, hw/acpi/piix4.c:PIIX4_PROC_BASE */ \ + WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \ + 0x0000, \ + 0xAF20, \ + 0xAFDF, \ + 0x0000, \ + 0x00C0, \ + ,, , TypeStatic) \ + /* 0xafe0-0xafe3 hole for ACPI.GPE0, hw/acpi/piix4.c:GPE_BASE */ \ + WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \ + 0x0000, \ + 0xAFE4, \ + 0xFFFF, \ + 0x0000, \ + 0x501C, \ + ,, , TypeStatic) Scope(\_SB) { Device(PCI0) { diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl index 9a43947..f3e5921 100644 --- a/hw/i386/q35-acpi-dsdt.dsl +++ b/hw/i386/q35-acpi-dsdt.dsl @@ -48,6 +48,14 @@ DefinitionBlock ( /**************************************************************** * PCI Bus definition ****************************************************************/ +#define BOARD_SPECIFIC_PCI_RESOURSES \ + WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, \ + 0x0000, \ + 0x0D00, \ + 0xFFFF, \ + 0x0000, \ + 0xF300, \ + ,, , TypeStatic) Scope(\_SB) { Device(PCI0) { -- 1.7.1