From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53898) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W1frN-0000eF-1l for qemu-devel@nongnu.org; Fri, 10 Jan 2014 12:27:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W1fr9-00033s-35 for qemu-devel@nongnu.org; Fri, 10 Jan 2014 12:27:04 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:44706) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W1fr8-00033K-TY for qemu-devel@nongnu.org; Fri, 10 Jan 2014 12:26:51 -0500 From: Peter Maydell Date: Fri, 10 Jan 2014 17:12:42 +0000 Message-Id: <1389373972-27686-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH 00/10] A64 SIMD patchset one: ld/st, C3.6.1..C3.6.7 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson This is an initial set of patches which make a start on SIMD (Neon) emulation in the A64 decoder. The patches implement all the SIMD load/store operations, provide a decoder skeleton for the SIMD dp instructions, and implement all the instructions in the ARM ARM's groupings C3.6.1 through C3.6.7. (It's more fluke than anything else that I ended up with all the first seven groupings in this set; they happened to all be easy small groupings. For some of the larger SIMD instruction groups I expect that we will end up implementing only some of the instructions in a group, in order to get more quickly to the useful milestone of "implement all the instructions gcc happens to emit today".) thanks -- PMM Alex Bennée (4): target-arm: A64: Add SIMD ld/st multiple target-arm: A64: Add decode skeleton for SIMD data processing insns target-arm: A64: Add SIMD copy operations target-arm: A64: Add SIMD modified immediate group Michael Matz (3): target-arm: A64: Add SIMD TBL/TBLX target-arm: A64: Add SIMD ZIP/UZP/TRN target-arm: A64: Add SIMD across-lanes instructions Peter Maydell (3): target-arm: A64: Add SIMD ld/st single target-arm: A64: Add SIMD EXT target-arm: A64: Add SIMD scalar copy instructions target-arm/helper-a64.c | 31 + target-arm/helper-a64.h | 1 + target-arm/translate-a64.c | 1440 +++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 1463 insertions(+), 9 deletions(-) -- 1.8.5