[Qemu-devel] [PATCH 04/10] target-arm: A64: Add SIMD EXT

[Peter Maydell <peter.maydell@linaro.org>]

Add support for the SIMD EXT instruction (the only one in its
group, C3.6.1).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate-a64.c | 62 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index fe5ad52..83ae222 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -4640,6 +4640,32 @@ static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
     }
 }
 
+static TCGv_i64 do_ext64(DisasContext *s, int leftreg, int leftelt,
+                         int rightreg, int rightelt, int pos)
+{
+    /* Extract 64 bits from the middle of two concatenated 64 bit
+     * vector register slices left:right. The extracted bits start
+     * at 'pos' bits into the right (least significant) side.
+     * For each slice, 'reg' indicates the vector register and
+     * 'elt' indicates which of the two 64 bit elements of it to use.
+     * The extracted value is returned in a TCGv_i64 temp.
+     */
+    TCGv_i64 tcg_res = tcg_temp_new_i64();
+    assert(pos >= 0 && pos < 64);
+
+    read_vec_element(s, tcg_res, rightreg, rightelt, MO_64);
+    if (pos != 0) {
+        TCGv_i64 tcg_left = tcg_temp_new_i64();
+
+        read_vec_element(s, tcg_left, leftreg, leftelt, MO_64);
+        tcg_gen_shli_i64(tcg_left, tcg_left, 64 - pos);
+        tcg_gen_shri_i64(tcg_res, tcg_res, pos);
+        tcg_gen_or_i64(tcg_res, tcg_res, tcg_left);
+        tcg_temp_free_i64(tcg_left);
+    }
+    return tcg_res;
+}
+
 /* C3.6.1 EXT
  *   31  30 29         24 23 22  21 20  16 15  14  11 10  9    5 4    0
  * +---+---+-------------+-----+---+------+---+------+---+------+------+
@@ -4648,7 +4674,41 @@ static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
  */
 static void disas_simd_ext(DisasContext *s, uint32_t insn)
 {
-    unsupported_encoding(s, insn);
+    int is_q = extract32(insn, 30, 1);
+    int op2 = extract32(insn, 22, 2);
+    int imm4 = extract32(insn, 11, 4);
+    int rm = extract32(insn, 16, 5);
+    int rn = extract32(insn, 5, 5);
+    int rd = extract32(insn, 0, 5);
+    int pos = imm4 << 3;
+    TCGv_i64 tcg_resl, tcg_resh;
+
+    if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) {
+        unallocated_encoding(s);
+        return;
+    }
+
+    /* Vd gets bits starting at pos bits into Vm:Vn. This is
+     * either extracting 128 bits from a 128:128 concatenation, or
+     * extracting 64 bits from a 64:64 concatenation.
+     */
+    if (!is_q) {
+        tcg_resl = do_ext64(s, rm, 0, rn, 0, pos);
+        tcg_resh = tcg_const_i64(0);
+    } else {
+        if (pos < 64) {
+            tcg_resl = do_ext64(s, rn, 1, rn, 0, pos);
+            tcg_resh = do_ext64(s, rm, 0, rn, 1, pos);
+        } else {
+            tcg_resl = do_ext64(s, rm, 0, rn, 1, pos - 64);
+            tcg_resh = do_ext64(s, rm, 1, rm, 0, pos - 64);
+        }
+    }
+
+    write_vec_element(s, tcg_resl, rd, 0, MO_64);
+    tcg_temp_free_i64(tcg_resl);
+    write_vec_element(s, tcg_resh, rd, 1, MO_64);
+    tcg_temp_free_i64(tcg_resh);
 }
 
 /* C3.6.2 TBL/TBX
-- 
1.8.5