From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50934) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W2eir-0001iC-Bw for qemu-devel@nongnu.org; Mon, 13 Jan 2014 05:26:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W2eip-00078d-7P for qemu-devel@nongnu.org; Mon, 13 Jan 2014 05:26:21 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:44771) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W2eio-00075W-V3 for qemu-devel@nongnu.org; Mon, 13 Jan 2014 05:26:19 -0500 From: Peter Maydell Date: Mon, 13 Jan 2014 10:26:16 +0000 Message-Id: <1389608776-32065-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH] target-arm: Switch ARMCPUInfo arrays to use terminator entries List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , patches@linaro.org Switch the ARMCPUInfo arrays in cpu.c and cpu64.c to use a terminator entry rather than looping based on ARRAY_SIZE. The latter causes compile warnings on some versions of gcc if the configure options happen to result in an empty array. Signed-off-by: Peter Maydell --- Edgar, I think this should fix the compile warning you're seeing with your gcc version. target-arm/cpu.c | 9 ++++++--- target-arm/cpu64.c | 15 ++++++--------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 408d207..c77a16c 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -980,6 +980,7 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "any", .initfn = arm_any_initfn }, #endif #endif + { .name = NULL } }; static Property arm_cpu_properties[] = { @@ -1043,11 +1044,13 @@ static const TypeInfo arm_cpu_type_info = { static void arm_cpu_register_types(void) { - int i; + const ARMCPUInfo *info = arm_cpus; type_register_static(&arm_cpu_type_info); - for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) { - cpu_register(&arm_cpus[i]); + + while (info->name) { + cpu_register(info); + info++; } } diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index 60acd24..a639c2e 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -58,7 +58,7 @@ static const ARMCPUInfo aarch64_cpus[] = { #ifdef CONFIG_USER_ONLY { .name = "any", .initfn = aarch64_any_initfn }, #endif - { .name = NULL } /* TODO: drop when we support more CPUs */ + { .name = NULL } }; static void aarch64_cpu_initfn(Object *obj) @@ -101,11 +101,6 @@ static void aarch64_cpu_register(const ARMCPUInfo *info) .class_init = info->class_init, }; - /* TODO: drop when we support more CPUs - all entries will have name set */ - if (!info->name) { - return; - } - type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); type_register(&type_info); g_free((void *)type_info.name); @@ -124,11 +119,13 @@ static const TypeInfo aarch64_cpu_type_info = { static void aarch64_cpu_register_types(void) { - int i; + const ARMCPUInfo *info = aarch64_cpus; type_register_static(&aarch64_cpu_type_info); - for (i = 0; i < ARRAY_SIZE(aarch64_cpus); i++) { - aarch64_cpu_register(&aarch64_cpus[i]); + + while (info->name) { + aarch64_cpu_register(info); + info++; } } -- 1.8.5