[Qemu-devel] [PATCH 0/9] target-arm: Add AArch32 ARMv8 VRINT instructions

[Qemu-devel] [PATCH 0/9] target-arm: Add AArch32 ARMv8 VRINT instructions

[Will Newton]

This series adds support for the floating-point and Advanced SIMD
versions of the VRINT family of instructions. 

Will Newton (9):
  target-arm: Move arm_rmode_to_sf to a shared location.
  target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM
  target-arm: Add support for AArch32 FP VRINTR
  target-arm: Add support for AArch32 FP VRINTZ
  target-arm: Add support for AArch32 FP VRINTX
  target-arm: Add support for AArch32 SIMD VRINTX
  target-arm: Add set_neon_rmode helper
  target-arm: Add support for AArch32 SIMD VRINTZ
  target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP and VRINTM

 target-arm/cpu.h           |   2 +
 target-arm/helper.c        |  45 ++++++++++++++
 target-arm/helper.h        |   1 +
 target-arm/translate-a64.c |  28 ---------
 target-arm/translate.c     | 145 +++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 193 insertions(+), 28 deletions(-)

-- 
1.8.1.4

[Qemu-devel] [PATCH 1/9] target-arm: Move arm_rmode_to_sf to a shared location.

[Will Newton]

This function will be needed for AArch32 ARMv8 support, so move it to
helper.c where it can be used by both targets. Also moves the code out
of line, but as it is quite a large function I don't believe this
should be a significant performance impact.

Signed-off-by: Will Newton <will.newton@linaro.org>
---
 target-arm/cpu.h           |  2 ++
 target-arm/helper.c        | 28 ++++++++++++++++++++++++++++
 target-arm/translate-a64.c | 28 ----------------------------
 3 files changed, 30 insertions(+), 28 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 198b6b8..383c582 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -496,6 +496,8 @@ enum arm_fprounding {
     FPROUNDING_ODD
 };
 
+int arm_rmode_to_sf(int rmode);
+
 enum arm_cpu_mode {
   ARM_CPU_MODE_USR = 0x10,
   ARM_CPU_MODE_FIQ = 0x11,
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c708f15..b1541b9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4418,3 +4418,31 @@ float64 HELPER(rintd)(float64 x, void *fp_status)
 
     return ret;
 }
+
+/* Convert ARM rounding mode to softfloat */
+int arm_rmode_to_sf(int rmode)
+{
+    switch (rmode) {
+    case FPROUNDING_TIEAWAY:
+        rmode = float_round_ties_away;
+        break;
+    case FPROUNDING_ODD:
+        /* FIXME: add support for TIEAWAY and ODD */
+        qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
+                      rmode);
+    case FPROUNDING_TIEEVEN:
+    default:
+        rmode = float_round_nearest_even;
+        break;
+    case FPROUNDING_POSINF:
+        rmode = float_round_up;
+        break;
+    case FPROUNDING_NEGINF:
+        rmode = float_round_down;
+        break;
+    case FPROUNDING_ZERO:
+        rmode = float_round_to_zero;
+        break;
+    }
+    return rmode;
+}
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index cf80c46..8effbe2 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3186,34 +3186,6 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
     }
 }
 
-/* Convert ARM rounding mode to softfloat */
-static inline int arm_rmode_to_sf(int rmode)
-{
-    switch (rmode) {
-    case FPROUNDING_TIEAWAY:
-        rmode = float_round_ties_away;
-        break;
-    case FPROUNDING_ODD:
-        /* FIXME: add support for TIEAWAY and ODD */
-        qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
-                      rmode);
-    case FPROUNDING_TIEEVEN:
-    default:
-        rmode = float_round_nearest_even;
-        break;
-    case FPROUNDING_POSINF:
-        rmode = float_round_up;
-        break;
-    case FPROUNDING_NEGINF:
-        rmode = float_round_down;
-        break;
-    case FPROUNDING_ZERO:
-        rmode = float_round_to_zero;
-        break;
-    }
-    return rmode;
-}
-
 static void handle_fp_compare(DisasContext *s, bool is_double,
                               unsigned int rn, unsigned int rm,
                               bool cmp_with_zero, bool signal_all_nans)
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH 1/9] target-arm: Move arm_rmode_to_sf to a shared location.

[Peter Maydell]

On 14 January 2014 16:43, Will Newton <will.newton@linaro.org> wrote:
> This function will be needed for AArch32 ARMv8 support, so move it to
> helper.c where it can be used by both targets. Also moves the code out
> of line, but as it is quite a large function I don't believe this
> should be a significant performance impact.

Well, it does mean that in the case where you pass the
function a constant input the compiler won't be able
to optimise it down to the correct constant output any
more, but there's only one case where we do that so I
don't think it matters much.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

[Qemu-devel] [PATCH 2/9] target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM

[Will Newton]

Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTM
instructions.

Signed-off-by: Will Newton <will.newton@linaro.org>
---
 target-arm/translate.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 8d240e1..f688f6d 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2759,6 +2759,51 @@ static int handle_vminmaxnm(uint32_t insn, uint32_t rd, uint32_t rn,
     return 0;
 }
 
+static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
+                        int rounding)
+{
+    TCGv_ptr fpst = get_fpstatus_ptr(0);
+    TCGv_i32 tcg_rmode;
+
+    tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
+    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+
+    if (dp) {
+        TCGv_i64 tcg_op;
+        TCGv_i64 tcg_res;
+        tcg_op = tcg_temp_new_i64();
+        tcg_res = tcg_temp_new_i64();
+        tcg_gen_ld_f64(tcg_op, cpu_env, vfp_reg_offset(dp, rm));
+        gen_helper_rintd(tcg_res, tcg_op, fpst);
+        tcg_gen_st_f64(tcg_res, cpu_env, vfp_reg_offset(dp, rd));
+        tcg_temp_free_i64(tcg_op);
+        tcg_temp_free_i64(tcg_res);
+    } else {
+        TCGv_i32 tcg_op;
+        TCGv_i32 tcg_res;
+        tcg_op = tcg_temp_new_i32();
+        tcg_res = tcg_temp_new_i32();
+        tcg_gen_ld_f32(tcg_op, cpu_env, vfp_reg_offset(dp, rm));
+        gen_helper_rints(tcg_res, tcg_op, fpst);
+        tcg_gen_st_f32(tcg_res, cpu_env, vfp_reg_offset(dp, rd));
+        tcg_temp_free_i32(tcg_op);
+        tcg_temp_free_i32(tcg_res);
+    }
+
+    gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+    tcg_temp_free_i32(tcg_rmode);
+
+    tcg_temp_free_ptr(fpst);
+    return 0;
+}
+
+static const uint8_t fp_decode_rm[] = {
+    FPROUNDING_TIEAWAY,
+    FPROUNDING_TIEEVEN,
+    FPROUNDING_POSINF,
+    FPROUNDING_NEGINF,
+};
+
 static int disas_vfp_v8_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
 {
     uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
@@ -2781,6 +2826,10 @@ static int disas_vfp_v8_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
         return handle_vsel(insn, rd, rn, rm, dp);
     } else if ((insn & 0x0fb00e10) == 0x0e800a00) {
         return handle_vminmaxnm(insn, rd, rn, rm, dp);
+    } else if ((insn & 0x0fbc0ed0) == 0x0eb80a40) {
+        /* VRINTA, VRINTN, VRINTP, VRINTM */
+        int rounding = fp_decode_rm[extract32(insn, 16, 2)];
+        return handle_vrint(insn, rd, rm, dp, rounding);
     }
     return 1;
 }
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH 2/9] target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM

[Peter Maydell]

On 14 January 2014 16:43, Will Newton <will.newton@linaro.org> wrote:
> Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTM
> instructions.


> +static const uint8_t fp_decode_rm[] = {
> +    FPROUNDING_TIEAWAY,
> +    FPROUNDING_TIEEVEN,
> +    FPROUNDING_POSINF,
> +    FPROUNDING_NEGINF,
> +};

This could use a comment:
/* Table for converting the most common AArch32 encoding of
 * rounding mode to arm_fprounding order (which matches the
 * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
 */

thanks
-- PMM

[Qemu-devel] [PATCH 3/9] target-arm: Add support for AArch32 FP VRINTR

[Will Newton]

Add support for the AArch32 floating-point VRINTR instruction.

Signed-off-by: Will Newton <will.newton@linaro.org>
---
 target-arm/translate.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index f688f6d..73e0e8d 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -3374,6 +3374,17 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
                         gen_vfp_F1_ld0(dp);
                         gen_vfp_cmpe(dp);
                         break;
+                    case 12: /* vrintr */
+                        if (dp) {
+                            TCGv_ptr fpst = get_fpstatus_ptr(0);
+                            gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
+                            tcg_temp_free_ptr(fpst);
+                        } else {
+                            TCGv_ptr fpst = get_fpstatus_ptr(0);
+                            gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
+                            tcg_temp_free_ptr(fpst);
+                        }
+                        break;
                     case 15: /* single<->double conversion */
                         if (dp)
                             gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH 3/9] target-arm: Add support for AArch32 FP VRINTR

[Peter Maydell]

On 14 January 2014 16:43, Will Newton <will.newton@linaro.org> wrote:
> Add support for the AArch32 floating-point VRINTR instruction.
>
> Signed-off-by: Will Newton <will.newton@linaro.org>
> ---
>  target-arm/translate.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index f688f6d..73e0e8d 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -3374,6 +3374,17 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
>                          gen_vfp_F1_ld0(dp);
>                          gen_vfp_cmpe(dp);
>                          break;
> +                    case 12: /* vrintr */
> +                        if (dp) {
> +                            TCGv_ptr fpst = get_fpstatus_ptr(0);
> +                            gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
> +                            tcg_temp_free_ptr(fpst);
> +                        } else {
> +                            TCGv_ptr fpst = get_fpstatus_ptr(0);
> +                            gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
> +                            tcg_temp_free_ptr(fpst);
> +                        }

Please pull the common setup/teardown of fpst out of the
two branches of this if():

    case 12: /* vrintr */
    {
         TCGv_ptr fpst = ...
         if (dp) {
                gen_helper_rintd(..)
         } else {
                gen_helper_rints(..)
         }
         tcg_temp_free...
         break;
    }

and similarly for other patches in this series (especially
where we're also doing setup/teardown of rounding mode).

thanks
-- PMM

[Qemu-devel] [PATCH 4/9] target-arm: Add support for AArch32 FP VRINTZ

[Will Newton]

Add support for the AArch32 floating-point VRINTZ instruction.

Signed-off-by: Will Newton <will.newton@linaro.org>
---
 target-arm/translate.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 73e0e8d..153d0e6 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -3385,6 +3385,27 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
                             tcg_temp_free_ptr(fpst);
                         }
                         break;
+                    case 13: /* vrintz */
+                        if (dp) {
+                            TCGv_ptr fpst = get_fpstatus_ptr(0);
+                            TCGv_i32 tcg_rmode;
+                            tcg_rmode = tcg_const_i32(float_round_to_zero);
+                            gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+                            gen_helper_rintd(cpu_F0d, cpu_F0d, fpst);
+                            gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+                            tcg_temp_free_i32(tcg_rmode);
+                            tcg_temp_free_ptr(fpst);
+                        } else {
+                            TCGv_ptr fpst = get_fpstatus_ptr(0);
+                            TCGv_i32 tcg_rmode;
+                            tcg_rmode = tcg_const_i32(float_round_to_zero);
+                            gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+                            gen_helper_rints(cpu_F0s, cpu_F0s, fpst);
+                            gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+                            tcg_temp_free_i32(tcg_rmode);
+                            tcg_temp_free_ptr(fpst);
+                        }
+                        break;
                     case 15: /* single<->double conversion */
                         if (dp)
                             gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
-- 
1.8.1.4

[Qemu-devel] [PATCH 5/9] target-arm: Add support for AArch32 FP VRINTX

[Will Newton]

Add support for the AArch32 floating-point VRINTX instruction.

Signed-off-by: Will Newton <will.newton@linaro.org>
---
 target-arm/translate.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 153d0e6..5108f6b 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -3406,6 +3406,17 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
                             tcg_temp_free_ptr(fpst);
                         }
                         break;
+                    case 14: /* vrintx */
+                        if (dp) {
+                            TCGv_ptr fpst = get_fpstatus_ptr(0);
+                            gen_helper_rintd_exact(cpu_F0d, cpu_F0d, fpst);
+                            tcg_temp_free_ptr(fpst);
+                        } else {
+                            TCGv_ptr fpst = get_fpstatus_ptr(0);
+                            gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpst);
+                            tcg_temp_free_ptr(fpst);
+                        }
+                        break;
                     case 15: /* single<->double conversion */
                         if (dp)
                             gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
-- 
1.8.1.4

[Qemu-devel] [PATCH 6/9] target-arm: Add support for AArch32 SIMD VRINTX

[Will Newton]

Add support for the AArch32 Advanced SIMD VRINTX instruction.

Signed-off-by: Will Newton <will.newton@linaro.org>
---
 target-arm/translate.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 5108f6b..b6d11db 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4709,6 +4709,7 @@ static const uint8_t neon_3r_sizes[] = {
 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
 #define NEON_2RM_VSHLL 38
+#define NEON_2RM_VRINTX 41
 #define NEON_2RM_VCVT_F16_F32 44
 #define NEON_2RM_VCVT_F32_F16 46
 #define NEON_2RM_VRECPE 56
@@ -4724,7 +4725,7 @@ static int neon_2rm_is_float_op(int op)
 {
     /* Return true if this neon 2reg-misc op is float-to-float */
     return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
-            op >= NEON_2RM_VRECPE_F);
+            op == NEON_2RM_VRINTX || op >= NEON_2RM_VRECPE_F);
 }
 
 /* Each entry in this array has bit n set if the insn allows
@@ -4768,6 +4769,7 @@ static const uint8_t neon_2rm_sizes[] = {
     [NEON_2RM_VMOVN] = 0x7,
     [NEON_2RM_VQMOVN] = 0x7,
     [NEON_2RM_VSHLL] = 0x7,
+    [NEON_2RM_VRINTX] = 0x4,
     [NEON_2RM_VCVT_F16_F32] = 0x2,
     [NEON_2RM_VCVT_F32_F16] = 0x2,
     [NEON_2RM_VRECPE] = 0x4,
@@ -6480,6 +6482,13 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
                             }
                             neon_store_reg(rm, pass, tmp2);
                             break;
+                        case NEON_2RM_VRINTX:
+                        {
+                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+                            gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpstatus);
+                            tcg_temp_free_ptr(fpstatus);
+                            break;
+                        }
                         case NEON_2RM_VRECPE:
                             gen_helper_recpe_u32(tmp, tmp, cpu_env);
                             break;
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH 6/9] target-arm: Add support for AArch32 SIMD VRINTX

[Peter Maydell]

On 14 January 2014 16:43, Will Newton <will.newton@linaro.org> wrote:
> Add support for the AArch32 Advanced SIMD VRINTX instruction.
>
> Signed-off-by: Will Newton <will.newton@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

[Qemu-devel] [PATCH 7/9] target-arm: Add set_neon_rmode helper

[Will Newton]

This helper sets the rounding mode in the standard_fp_status word to
allow NEON instructions to modify the rounding mode whilst using the
standard FPSCR values for everything else.

Signed-off-by: Will Newton <will.newton@linaro.org>
---
 target-arm/helper.c | 17 +++++++++++++++++
 target-arm/helper.h |  1 +
 2 files changed, 18 insertions(+)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index b1541b9..ca5b000 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4048,6 +4048,23 @@ uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
     return prev_rmode;
 }
 
+/* Set the current fp rounding mode in the standard fp status and return
+ * the old one. This is for NEON instructions that need to change the
+ * rounding mode but wish to use the standard FPSCR values for everything
+ * else. Always set the rounding mode back to the correct value after
+ * modifying it.
+ * The argument is a softfloat float_round_ value.
+ */
+uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
+{
+    float_status *fp_status = &env->vfp.standard_fp_status;
+
+    uint32_t prev_rmode = get_float_rounding_mode(fp_status);
+    set_float_rounding_mode(rmode, fp_status);
+
+    return prev_rmode;
+}
+
 /* Half precision conversions.  */
 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
 {
diff --git a/target-arm/helper.h b/target-arm/helper.h
index 70872df..71b8411 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -149,6 +149,7 @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
 DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
 
 DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, env)
+DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
 
 DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env)
 DEF_HELPER_2(vfp_fcvt_f32_to_f16, i32, f32, env)
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH 7/9] target-arm: Add set_neon_rmode helper

[Peter Maydell]

On 14 January 2014 16:43, Will Newton <will.newton@linaro.org> wrote:
> This helper sets the rounding mode in the standard_fp_status word to
> allow NEON instructions to modify the rounding mode whilst using the
> standard FPSCR values for everything else.
>
> Signed-off-by: Will Newton <will.newton@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

[Qemu-devel] [PATCH 8/9] target-arm: Add support for AArch32 SIMD VRINTZ

[Will Newton]

Add support for the AArch32 Advanced SIMD VRINTZ instruction.

Signed-off-by: Will Newton <will.newton@linaro.org>
---
 target-arm/translate.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index b6d11db..16242d3 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4710,6 +4710,7 @@ static const uint8_t neon_3r_sizes[] = {
 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
 #define NEON_2RM_VSHLL 38
 #define NEON_2RM_VRINTX 41
+#define NEON_2RM_VRINTZ 43
 #define NEON_2RM_VCVT_F16_F32 44
 #define NEON_2RM_VCVT_F32_F16 46
 #define NEON_2RM_VRECPE 56
@@ -4725,7 +4726,8 @@ static int neon_2rm_is_float_op(int op)
 {
     /* Return true if this neon 2reg-misc op is float-to-float */
     return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
-            op == NEON_2RM_VRINTX || op >= NEON_2RM_VRECPE_F);
+            op == NEON_2RM_VRINTX || op == NEON_2RM_VRINTZ ||
+            op >= NEON_2RM_VRECPE_F);
 }
 
 /* Each entry in this array has bit n set if the insn allows
@@ -4770,6 +4772,7 @@ static const uint8_t neon_2rm_sizes[] = {
     [NEON_2RM_VQMOVN] = 0x7,
     [NEON_2RM_VSHLL] = 0x7,
     [NEON_2RM_VRINTX] = 0x4,
+    [NEON_2RM_VRINTZ] = 0x4,
     [NEON_2RM_VCVT_F16_F32] = 0x2,
     [NEON_2RM_VCVT_F32_F16] = 0x2,
     [NEON_2RM_VRECPE] = 0x4,
@@ -6489,6 +6492,20 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
                             tcg_temp_free_ptr(fpstatus);
                             break;
                         }
+                        case NEON_2RM_VRINTZ:
+                        {
+                            TCGv_i32 tcg_rmode;
+                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+                            tcg_rmode = tcg_const_i32(float_round_to_zero);
+                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
+                                                      cpu_env);
+                            gen_helper_rints(cpu_F0s, cpu_F0s, fpstatus);
+                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
+                                                      cpu_env);
+                            tcg_temp_free_ptr(fpstatus);
+                            tcg_temp_free_i32(tcg_rmode);
+                            break;
+                        }
                         case NEON_2RM_VRECPE:
                             gen_helper_recpe_u32(tmp, tmp, cpu_env);
                             break;
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH 8/9] target-arm: Add support for AArch32 SIMD VRINTZ

[Peter Maydell]

On 14 January 2014 16:43, Will Newton <will.newton@linaro.org> wrote:
> Add support for the AArch32 Advanced SIMD VRINTZ instruction.
>
> Signed-off-by: Will Newton <will.newton@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

[Qemu-devel] [PATCH 9/9] target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP and VRINTM

[Will Newton]

Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP
and VRINTM instructions.

Signed-off-by: Will Newton <will.newton@linaro.org>
---
 target-arm/translate.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 16242d3..5564cb9 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4709,10 +4709,14 @@ static const uint8_t neon_3r_sizes[] = {
 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
 #define NEON_2RM_VSHLL 38
+#define NEON_2RM_VRINTN 40
 #define NEON_2RM_VRINTX 41
+#define NEON_2RM_VRINTA 42
 #define NEON_2RM_VRINTZ 43
 #define NEON_2RM_VCVT_F16_F32 44
+#define NEON_2RM_VRINTM 45
 #define NEON_2RM_VCVT_F32_F16 46
+#define NEON_2RM_VRINTP 47
 #define NEON_2RM_VRECPE 56
 #define NEON_2RM_VRSQRTE 57
 #define NEON_2RM_VRECPE_F 58
@@ -4726,7 +4730,8 @@ static int neon_2rm_is_float_op(int op)
 {
     /* Return true if this neon 2reg-misc op is float-to-float */
     return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
-            op == NEON_2RM_VRINTX || op == NEON_2RM_VRINTZ ||
+            (op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) ||
+            op == NEON_2RM_VRINTM || op == NEON_2RM_VRINTP ||
             op >= NEON_2RM_VRECPE_F);
 }
 
@@ -4771,10 +4776,14 @@ static const uint8_t neon_2rm_sizes[] = {
     [NEON_2RM_VMOVN] = 0x7,
     [NEON_2RM_VQMOVN] = 0x7,
     [NEON_2RM_VSHLL] = 0x7,
+    [NEON_2RM_VRINTN] = 0x4,
     [NEON_2RM_VRINTX] = 0x4,
+    [NEON_2RM_VRINTA] = 0x4,
     [NEON_2RM_VRINTZ] = 0x4,
     [NEON_2RM_VCVT_F16_F32] = 0x2,
+    [NEON_2RM_VRINTM] = 0x4,
     [NEON_2RM_VCVT_F32_F16] = 0x2,
+    [NEON_2RM_VRINTP] = 0x4,
     [NEON_2RM_VRECPE] = 0x4,
     [NEON_2RM_VRSQRTE] = 0x4,
     [NEON_2RM_VRECPE_F] = 0x4,
@@ -6485,6 +6494,24 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
                             }
                             neon_store_reg(rm, pass, tmp2);
                             break;
+                        case NEON_2RM_VRINTN:
+                        case NEON_2RM_VRINTA:
+                        case NEON_2RM_VRINTM:
+                        case NEON_2RM_VRINTP:
+                        {
+                            TCGv_i32 tcg_rmode;
+                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+                            int rmode = fp_decode_rm[((op & 0x6) >> 1) ^ 1];
+                            tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
+                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
+                                                      cpu_env);
+                            gen_helper_rints(cpu_F0s, cpu_F0s, fpstatus);
+                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
+                                                      cpu_env);
+                            tcg_temp_free_ptr(fpstatus);
+                            tcg_temp_free_i32(tcg_rmode);
+                            break;
+                        }
                         case NEON_2RM_VRINTX:
                         {
                             TCGv_ptr fpstatus = get_fpstatus_ptr(1);
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH 9/9] target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP and VRINTM

[Peter Maydell]

On 14 January 2014 16:43, Will Newton <will.newton@linaro.org> wrote:
> Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP
> and VRINTM instructions.

> +                        case NEON_2RM_VRINTN:
> +                        case NEON_2RM_VRINTA:
> +                        case NEON_2RM_VRINTM:
> +                        case NEON_2RM_VRINTP:
> +                        {
> +                            TCGv_i32 tcg_rmode;
> +                            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
> +                            int rmode = fp_decode_rm[((op & 0x6) >> 1) ^ 1];
> +                            tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
> +                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
> +                                                      cpu_env);
> +                            gen_helper_rints(cpu_F0s, cpu_F0s, fpstatus);
> +                            gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
> +                                                      cpu_env);
> +                            tcg_temp_free_ptr(fpstatus);
> +                            tcg_temp_free_i32(tcg_rmode);
> +                            break;

This is almost exactly the same as the VRINTZ case so I think
it would be nicer to combine them:
    if (op == NEON_2RM_VRINTZ) {
        rmode = FPROUNDING_ZERO;
    } else {
        rmode = fp_decode_rm[...];
    }

&c.

thanks
-- PMM