From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41161) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W375W-0002BA-GJ for qemu-devel@nongnu.org; Tue, 14 Jan 2014 11:43:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W375P-0001Kd-Jb for qemu-devel@nongnu.org; Tue, 14 Jan 2014 11:43:38 -0500 Received: from mail-wi0-f178.google.com ([209.85.212.178]:35752) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W375P-0001KV-D2 for qemu-devel@nongnu.org; Tue, 14 Jan 2014 11:43:31 -0500 Received: by mail-wi0-f178.google.com with SMTP id cc10so987271wib.11 for ; Tue, 14 Jan 2014 08:43:30 -0800 (PST) From: Will Newton Date: Tue, 14 Jan 2014 16:43:09 +0000 Message-Id: <1389717790-30860-9-git-send-email-will.newton@linaro.org> In-Reply-To: <1389717790-30860-1-git-send-email-will.newton@linaro.org> References: <1389717790-30860-1-git-send-email-will.newton@linaro.org> Subject: [Qemu-devel] [PATCH 8/9] target-arm: Add support for AArch32 SIMD VRINTZ List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell Add support for the AArch32 Advanced SIMD VRINTZ instruction. Signed-off-by: Will Newton --- target-arm/translate.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index b6d11db..16242d3 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4710,6 +4710,7 @@ static const uint8_t neon_3r_sizes[] = { #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */ #define NEON_2RM_VSHLL 38 #define NEON_2RM_VRINTX 41 +#define NEON_2RM_VRINTZ 43 #define NEON_2RM_VCVT_F16_F32 44 #define NEON_2RM_VCVT_F32_F16 46 #define NEON_2RM_VRECPE 56 @@ -4725,7 +4726,8 @@ static int neon_2rm_is_float_op(int op) { /* Return true if this neon 2reg-misc op is float-to-float */ return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F || - op == NEON_2RM_VRINTX || op >= NEON_2RM_VRECPE_F); + op == NEON_2RM_VRINTX || op == NEON_2RM_VRINTZ || + op >= NEON_2RM_VRECPE_F); } /* Each entry in this array has bit n set if the insn allows @@ -4770,6 +4772,7 @@ static const uint8_t neon_2rm_sizes[] = { [NEON_2RM_VQMOVN] = 0x7, [NEON_2RM_VSHLL] = 0x7, [NEON_2RM_VRINTX] = 0x4, + [NEON_2RM_VRINTZ] = 0x4, [NEON_2RM_VCVT_F16_F32] = 0x2, [NEON_2RM_VCVT_F32_F16] = 0x2, [NEON_2RM_VRECPE] = 0x4, @@ -6489,6 +6492,20 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins tcg_temp_free_ptr(fpstatus); break; } + case NEON_2RM_VRINTZ: + { + TCGv_i32 tcg_rmode; + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + tcg_rmode = tcg_const_i32(float_round_to_zero); + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, + cpu_env); + gen_helper_rints(cpu_F0s, cpu_F0s, fpstatus); + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, + cpu_env); + tcg_temp_free_ptr(fpstatus); + tcg_temp_free_i32(tcg_rmode); + break; + } case NEON_2RM_VRECPE: gen_helper_recpe_u32(tmp, tmp, cpu_env); break; -- 1.8.1.4