From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58574) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W3RBc-000170-KH for qemu-devel@nongnu.org; Wed, 15 Jan 2014 09:11:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W3RBW-0006Zv-LK for qemu-devel@nongnu.org; Wed, 15 Jan 2014 09:11:16 -0500 From: Tom Musta Date: Wed, 15 Jan 2014 08:10:37 -0600 Message-Id: <1389795045-5504-11-git-send-email-tommusta@gmail.com> In-Reply-To: <1389795045-5504-1-git-send-email-tommusta@gmail.com> References: <1389795045-5504-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [V7 PATCH 10/18] target-ppc: VSX Stage 4: Add xssqrtsp List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Tom Musta , qemu-ppc@nongnu.org This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp) instruction. The existing VSX_SQRT() macro is modified to support rounding of the intermediate double-precision result to single-precision. Signed-off-by: Tom Musta Reviewed-by: Richard Henderson --- V2: Updated conversion to single precision range. target-ppc/fpu_helper.c | 13 +++++++++---- target-ppc/helper.h | 1 + target-ppc/translate.c | 2 ++ 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index ac52c23..fec9d1b 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1969,7 +1969,7 @@ VSX_RE(xvresp, 4, float32, f32, 0, 0) * fld - vsr_t field (f32 or f64) * sfprf - set FPRF */ -#define VSX_SQRT(op, nels, tp, fld, sfprf) \ +#define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \ void helper_##op(CPUPPCState *env, uint32_t opcode) \ { \ ppc_vsr_t xt, xb; \ @@ -1993,6 +1993,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ } \ } \ \ + if (r2sp) { \ + xt.fld[i] = helper_frsp(env, xt.fld[i]); \ + } \ + \ if (sfprf) { \ helper_compute_fprf(env, xt.fld[i], sfprf); \ } \ @@ -2002,9 +2006,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ helper_float_check_status(env); \ } -VSX_SQRT(xssqrtdp, 1, float64, f64, 1) -VSX_SQRT(xvsqrtdp, 2, float64, f64, 0) -VSX_SQRT(xvsqrtsp, 4, float32, f32, 0) +VSX_SQRT(xssqrtdp, 1, float64, f64, 1, 0) +VSX_SQRT(xssqrtsp, 1, float64, f64, 1, 1) +VSX_SQRT(xvsqrtdp, 2, float64, f64, 0, 0) +VSX_SQRT(xvsqrtsp, 4, float32, f32, 0, 0) /* VSX_RSQRTE - VSX floating point reciprocal square root estimate * op - instruction mnemonic diff --git a/target-ppc/helper.h b/target-ppc/helper.h index b1cf3c0..0192043 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -291,6 +291,7 @@ DEF_HELPER_2(xssubsp, void, env, i32) DEF_HELPER_2(xsmulsp, void, env, i32) DEF_HELPER_2(xsdivsp, void, env, i32) DEF_HELPER_2(xsresp, void, env, i32) +DEF_HELPER_2(xssqrtsp, void, env, i32) DEF_HELPER_2(xvadddp, void, env, i32) DEF_HELPER_2(xvsubdp, void, env, i32) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 3108a29..f4c1f42 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7363,6 +7363,7 @@ GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) +GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) @@ -10175,6 +10176,7 @@ GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207), GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207), GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207), GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207), +GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207), GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX), -- 1.7.1