From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58760) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W3RBo-0001U2-Dz for qemu-devel@nongnu.org; Wed, 15 Jan 2014 09:11:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W3RBg-0006nH-1D for qemu-devel@nongnu.org; Wed, 15 Jan 2014 09:11:28 -0500 From: Tom Musta Date: Wed, 15 Jan 2014 08:10:43 -0600 Message-Id: <1389795045-5504-17-git-send-email-tommusta@gmail.com> In-Reply-To: <1389795045-5504-1-git-send-email-tommusta@gmail.com> References: <1389795045-5504-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [V7 PATCH 16/18] target-ppc: Floating Merge Word Instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Tom Musta , qemu-ppc@nongnu.org This patch adds the Floating Merge Even Word (fmrgew) and Floating Merge Odd Word (fmrgow) instructions. Signed-off-by: Tom Musta --- V6: New. V7: Optimized fmrgow to better use deposit (per Richard Henderson's review). target-ppc/translate.c | 28 ++++++++++++++++++++++++++++ 1 files changed, 28 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index cd47d3e..8ff5d72 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2294,6 +2294,32 @@ static void gen_fcpsgn(DisasContext *ctx) gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); } +static void gen_fmrgew(DisasContext *ctx) +{ + TCGv_i64 b0; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + b0 = tcg_temp_new_i64(); + tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32); + tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], + b0, 0, 32); + tcg_temp_free_i64(b0); +} + +static void gen_fmrgow(DisasContext *ctx) +{ + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], + cpu_fpr[rB(ctx->opcode)], + cpu_fpr[rA(ctx->opcode)], + 32, 32); +} + /*** Floating-Point status & ctrl register ***/ /* mcrfs */ @@ -9414,6 +9440,8 @@ GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT), GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT), GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205), +GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207), GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), -- 1.7.1