[Qemu-devel] [PATCH 0/8] target-arm: A64 Neon instructions, set 2

[Peter Maydell <peter.maydell@linaro.org>]

This is the second set of patches for A64 Neon. The last patch
set did a complete coverage of some of the smaller and simpler
instruction groupings; this patch set attacks a few of the
larger groupings (3-same; scalar 3-same; 3-different; shift-imm;
scalar shift-imm) and doesn't attempt complete coverage of them.
My rule of thumb was to (a) implement enough instructions to
demonstrate that the general decode and set of sub-functions/loops
was adequate (b) aim to cover at least as much as the SuSE tree.

Remaining things in SuSE 1.6 tree not yet implemented:
 3-reg-same MLA, MLS, MUL, PMUL, SMAX, UMAX, SMIN, UMIN,
            SSHL, USHL, SQSHL, UQSHL, SRSHL, URSHL
 2-reg-misc XTN, FABS, FNEG, NOT

thanks
-- PMM

Alex Bennée (2):
  target-arm: A64: Add logic ops from SIMD 3 same group
  target-arm: A64: Add SIMD shift by immediate

Peter Maydell (6):
  target-arm: A64: Add SIMD three-different multiply accumulate insns
  target-arm: A64: Add SIMD three-different ABDL instructions
  target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
  target-arm: A64: Add top level decode for SIMD 3-same group
  target-arm: A64: Add integer ops from SIMD 3-same group
  target-arm: A64: Add simple SIMD 3-same floating point ops

 target-arm/translate-a64.c | 1190 +++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 1186 insertions(+), 4 deletions(-)

-- 
1.8.5