From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58647) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W5ERP-0005LC-Nj for qemu-devel@nongnu.org; Mon, 20 Jan 2014 07:59:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W5ERH-0006zo-HH for qemu-devel@nongnu.org; Mon, 20 Jan 2014 07:58:59 -0500 Received: from mx1.redhat.com ([209.132.183.28]:2975) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W5ERH-0006yb-9c for qemu-devel@nongnu.org; Mon, 20 Jan 2014 07:58:51 -0500 Message-ID: <1390222725.11527.46.camel@nilsson.home.kraxel.org> From: Gerd Hoffmann Date: Mon, 20 Jan 2014 13:58:45 +0100 In-Reply-To: <20140120112345.GA11565@redhat.com> References: <1387185088-16811-1-git-send-email-kraxel@redhat.com> <20131216115401.GA19233@redhat.com> <1387201577.28883.38.camel@nilsson.home.kraxel.org> <20131216192843.GB21330@redhat.com> <1387277686.12500.35.camel@nilsson.home.kraxel.org> <20131217115936.GA30168@redhat.com> <1387302966.12500.85.camel@nilsson.home.kraxel.org> <20140120112345.GA11565@redhat.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2] x86: gigabyte alignment for ram List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: qemu-devel@nongnu.org, Anthony Liguori On Mo, 2014-01-20 at 13:23 +0200, Michael S. Tsirkin wrote: > On Tue, Dec 17, 2013 at 06:56:06PM +0100, Gerd Hoffmann wrote: > > > I merged your patch but split it: q35 is separate and piix > > > is separate. Would you like me to drop the q35 part then? > > > > If you are fine with q35 having only 2G lowmem keep it. It's safe. > > > > We can sort the mmconfig setup afterwards, then check if (and how) we'll > > transition to 3G lowmem. Maybe we simply don't after all, with the > > world moving to 64bit it doesn't matter that much whenever memory is > > mapped above or below 4g. And for old 32bit guests there is always the > > option to stick with piix which continues to offers up to 3.5G lowmem. > > > > cheers, > > Gerd > > > > Any update here? No time to investigate yet, still playing catch-up after xmas holidays & being sick. > I'm worried 2G lowmem is a bit too aggressive, PAE still exists. piix (with up to 3.5g lowmem) exists too ;) > If we want to support old bios, one way would be to add > a new register to enable 3g lowmem. Do we really want do this (allow guest change RAM mapping)? I think we should: (1) reserve mmconf xbar as motherboard ressource, so it can live within PCI0._CRS (2) make PCI0._CRS start at end of lowmem, like it does on piix Then maybe: (3) update seabios to place xbar somewhere else (4) adjust memory layout. (1)+(2) are useful anyway. (3)+(4) would allow for 3g lowmem, and obviously have some compatibility issues: doing (4) requires a seabios update. cheers, Gerd