From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51127) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W5hgn-0005FJ-QF for qemu-devel@nongnu.org; Tue, 21 Jan 2014 15:12:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W5hgm-0007fC-Ng for qemu-devel@nongnu.org; Tue, 21 Jan 2014 15:12:49 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:44951) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W5hgm-0007WW-GR for qemu-devel@nongnu.org; Tue, 21 Jan 2014 15:12:48 -0500 From: Peter Maydell Date: Tue, 21 Jan 2014 20:12:06 +0000 Message-Id: <1390335150-13470-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 00/24] target-arm: implement some AArch64 system registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Claudio Fontana , Dirk Mueller , Will Newton , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson This is a chunk of patches which make a start on the AArch64 system emulation. Specifically, most of them are providing AArch64 system registers used by Linux as it boots. There are also a few patches adding extra instruction support, like the system mode store-exclusives and MSR-immediate. This together with another half-dozen or so rather hackier patches is sufficient to get an AArch64 mach-virt kernel image to boot enough to send messages to the UART (before it gets roadblocked by interrupts and exceptions being totally broken). [if you really like living on the bleeding edge you can find the version with the extra hacks here: git://git.linaro.org/people/peter.maydell/qemu-arm.git a64-system though it may well be broken at any given moment since it's my working tree.] If people would rather wait for a more complete and vaguely functional system mode before starting review that's fine, but I figured since these patches are all I think correct and clean enough to commit I might as well send them out now. A git branch with this patchset is: git://git.linaro.org/people/peter.maydell/qemu-arm.git a64-system-sysregs thanks -- PMM Peter Maydell (24): target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs target-arm: Define names for SCTLR bits target-arm: Restrict check_ap() use of S and R bits to v6 and earlier target-arm: Log bad system register accesses with LOG_UNIMP target-arm: Add exception level to the AArch64 TB flags target-arm: A64: Implement store-exclusive for system mode target-arm: A64: Make cache ID registers visible to AArch64 target-arm: A64: Implement MSR (immediate) instructions target-arm: Implement AArch64 CurrentEL sysreg target-arm: Implement AArch64 MIDR_EL1 target-arm: Implement AArch64 DAIF system register target-arm: Implement AArch64 cache invalidate/clean ops target-arm: Implement AArch64 TLB invalidate ops target-arm: Implement AArch64 dummy MDSCR_EL1 target-arm: Implement AArch64 memory attribute registers target-arm: Implement AArch64 SCTLR_EL1 target-arm: Implement AArch64 TCR_EL1 target-arm: Implement AArch64 VBAR_EL1 target-arm: Implement AArch64 TTBR* target-arm: Implement AArch64 MPIDR target-arm: Implement AArch64 generic timers target-arm: Implement AArch64 ID and feature registers target-arm: Implement AArch64 dummy breakpoint and watchpoint registers target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI hw/arm/pxa2xx.c | 2 +- target-arm/cpu-qom.h | 10 + target-arm/cpu.c | 4 +- target-arm/cpu.h | 92 ++++++-- target-arm/cpu64.c | 1 + target-arm/helper.c | 565 +++++++++++++++++++++++++++++++++++++-------- target-arm/helper.h | 2 + target-arm/kvm-consts.h | 16 +- target-arm/op_helper.c | 25 ++ target-arm/translate-a64.c | 106 ++++++++- target-arm/translate.c | 13 ++ 11 files changed, 713 insertions(+), 123 deletions(-) -- 1.8.5