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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
	patches@linaro.org, "Michael Matz" <matz@suse.de>,
	"Alexander Graf" <agraf@suse.de>,
	"Claudio Fontana" <claudio.fontana@linaro.org>,
	"Dirk Mueller" <dmueller@suse.de>,
	"Will Newton" <will.newton@linaro.org>,
	"Laurent Desnogues" <laurent.desnogues@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	kvmarm@lists.cs.columbia.edu,
	"Christoffer Dall" <christoffer.dall@linaro.org>,
	"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH 01/24] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs
Date: Tue, 21 Jan 2014 20:12:07 +0000	[thread overview]
Message-ID: <1390335150-13470-2-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1390335150-13470-1-git-send-email-peter.maydell@linaro.org>

Extend the set of CPUs for which we provide a QEMU_KVM_ARM_TARGET_*
constant to include all the ones currently supported by the kernel
headers we are using.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/kvm-consts.h | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/target-arm/kvm-consts.h b/target-arm/kvm-consts.h
index 0e7f889..c8dfdd6 100644
--- a/target-arm/kvm-consts.h
+++ b/target-arm/kvm-consts.h
@@ -50,15 +50,29 @@ MISMATCH_CHECK(PSCI_FN_CPU_OFF, KVM_PSCI_FN_CPU_OFF)
 MISMATCH_CHECK(PSCI_FN_CPU_ON, KVM_PSCI_FN_CPU_ON)
 MISMATCH_CHECK(PSCI_FN_MIGRATE, KVM_PSCI_FN_MIGRATE)
 
+/* Note that KVM uses overlapping values for AArch32 and AArch64
+ * target CPU numbers. AArch32 targets:
+ */
 #define QEMU_KVM_ARM_TARGET_CORTEX_A15 0
+#define QEMU_KVM_ARM_TARGET_CORTEX_A7 1
+
+/* AArch64 targets: */
+#define QEMU_KVM_ARM_TARGET_AEM_V8 0
+#define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1
+#define QEMU_KVM_ARM_TARGET_CORTEX_A57 2
 
 /* There's no kernel define for this: sentinel value which
  * matches no KVM target value for either 64 or 32 bit
  */
 #define QEMU_KVM_ARM_TARGET_NONE UINT_MAX
 
-#ifndef TARGET_AARCH64
+#ifdef TARGET_AARCH64
+MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_ARM_V8)
+MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8)
+MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57)
+#else
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15)
+MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7)
 #endif
 
 #define CP_REG_ARM64                   0x6000000000000000ULL
-- 
1.8.5

  reply	other threads:[~2014-01-21 20:12 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-01-21 20:12 [Qemu-devel] [PATCH 00/24] target-arm: implement some AArch64 system registers Peter Maydell
2014-01-21 20:12 ` Peter Maydell [this message]
2014-01-23 12:04   ` [Qemu-devel] [PATCH 01/24] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 02/24] target-arm: Define names for SCTLR bits Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 03/24] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier Peter Maydell
2014-01-24 23:28   ` Peter Crosthwaite
2014-01-21 20:12 ` [Qemu-devel] [PATCH 04/24] target-arm: Log bad system register accesses with LOG_UNIMP Peter Maydell
2014-01-24 23:30   ` Peter Crosthwaite
2014-01-21 20:12 ` [Qemu-devel] [PATCH 05/24] target-arm: Add exception level to the AArch64 TB flags Peter Maydell
2014-01-28  1:28   ` Peter Crosthwaite
2014-01-28  8:42     ` Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 06/24] target-arm: A64: Implement store-exclusive for system mode Peter Maydell
2014-01-22  2:19   ` Hu Tao
2014-01-22 10:42     ` Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 07/24] target-arm: A64: Make cache ID registers visible to AArch64 Peter Maydell
2014-01-28  1:46   ` Peter Crosthwaite
2014-01-28  8:45     ` Peter Maydell
2014-01-28 14:05       ` Peter Crosthwaite
2014-01-28 18:12         ` Peter Maydell
2014-01-28 18:16           ` Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 08/24] target-arm: A64: Implement MSR (immediate) instructions Peter Maydell
2014-01-22  3:10   ` Hu Tao
2014-01-22 10:48     ` Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 09/24] target-arm: Implement AArch64 CurrentEL sysreg Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 10/24] target-arm: Implement AArch64 MIDR_EL1 Peter Maydell
2014-01-28  1:50   ` Peter Crosthwaite
2014-01-21 20:12 ` [Qemu-devel] [PATCH 11/24] target-arm: Implement AArch64 DAIF system register Peter Maydell
2014-01-28  1:54   ` Peter Crosthwaite
2014-01-28  8:46     ` Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 12/24] target-arm: Implement AArch64 cache invalidate/clean ops Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 13/24] target-arm: Implement AArch64 TLB invalidate ops Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 14/24] target-arm: Implement AArch64 dummy MDSCR_EL1 Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 15/24] target-arm: Implement AArch64 memory attribute registers Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 16/24] target-arm: Implement AArch64 SCTLR_EL1 Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 17/24] target-arm: Implement AArch64 TCR_EL1 Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 18/24] target-arm: Implement AArch64 VBAR_EL1 Peter Maydell
2014-01-25  0:11   ` Peter Crosthwaite
2014-01-21 20:12 ` [Qemu-devel] [PATCH 19/24] target-arm: Implement AArch64 TTBR* Peter Maydell
2014-01-24 23:44   ` Peter Crosthwaite
2014-01-25  0:09     ` Peter Maydell
2014-01-28  2:07       ` Peter Crosthwaite
2014-01-28  8:58         ` Peter Maydell
2014-01-28 11:42     ` Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 20/24] target-arm: Implement AArch64 MPIDR Peter Maydell
2014-01-25  0:12   ` Peter Crosthwaite
2014-01-21 20:12 ` [Qemu-devel] [PATCH 21/24] target-arm: Implement AArch64 generic timers Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 22/24] target-arm: Implement AArch64 ID and feature registers Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 23/24] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers Peter Maydell
2014-01-21 20:12 ` [Qemu-devel] [PATCH 24/24] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI Peter Maydell

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